FPGA Architecture
This page will document the high-level architecture of the FPGA and relate it to the Verilog codebase hierarchy. Since the source codebase appears as just a flat list of filenames, some documentation on its structure is required to facilitate understanding. In the coming weeks (as of 2/3/2021), documentation on the Verilog sub-blocks will also be added here
A conceptual view of the FPGA image is shown above. The top level of the design is denoted (1), which corresponds to the top level Verilog file. The interface to the Semtech SX1257 flexible radio IC (we call it "SDR" in the figure above) is on the left, while the SPI interfaces to the radio (SDR IC and digitally tunable capacitor (DTC) set) and MCU are shown at the top and bottom of the right, respectively. Radio receive signal flow is from left to right, while radio transmit signal flow is from right to left.
- Block (2): CIC (Cascaded Integrator-Comb Filter) plus decimation-by-8.
- Performs a low-resource count initial filtering and decimation of the incoming 1-b bitstream.
- There is one of these for each of I and Q RX channels.
- Block (3): IIR Very Low-Pass Filter plus decimation-by-8.
- Extracts a near-DC signal to drive the transmit leakage cancellation algorithm.
- There is one of these for each of I and Q RX channels.
- Block (4): Channel Filter
- Is a dual second-order-resonator IIR filter centered at the tag backscatter link frequency (BLF).
- This filter passes information from the UHF RFID tag while rejecting other radio signals.
- Block (5): Clock and Data Recovery
- Recovers the data clock from the incoming UHF RFID waveform and uses this to sample the data.
- Pseudo-matched-filter integrate-and-dump circuits, along with CRC and magnitude detection are implemented in the data recovery.
- Recovered tag response bits, waveform I/Q magnitudes, and error codes are stored in Radio SRAM (15).
- Block (17): Waveform Record
- Takes raw RX I,Q data and dumps it into RAM. This is currently disabled to save resources.
- Nearly 1ms of data can be obtained for advanced tag localization techniques.
- Block (18): Waveform SRAM
- A big memory to hold raw I,Q RX data. This is currently disabled to save resources.
- Block (6): TX Cancel
- This block takes near-DC data from the RX Chain and uses it to drive the SPI controller.
- TX Cancel uses gradient descent to actuate the PCB digitally tunable capacitors to minimize the block (3) output.
- Minimizing the block 3 output effectively minimizes transmit leakage to the radio receiver input.
- Block (10): TX Generator
- Generates UHF RFID reader baseband TX waveforms based on contents of Radio SRAM and Radio FSM.
- Block (11): Sigma-Delta Modulator
- Converts the TX Generator output into a format accepted by the SX1257 flexible radio IC (we denote this IC as "SDR" here).
- Block (12): Zero Generator
- Since UHF RFID works with a DSB-ASK waveform, complex transmit data is not required.
- Therefore, to save resources, a simple up-down counter is used to generate a DC offset on the data Q line.
- This offset counters the onboard DC offset in the SX1257 DAC/ TX baseband circuitry.
- Block (13): Clock and Reset Management
- Performs clock division and buffering.
- Converts asynchronous resets into resets with timed deasserts.
- Block (14): Radio FSM
- Finite state machine that controls the radio during intervals with limited turnaround time.
- Executes a set of UHF RFID reader commands and receives tag data, then passes control back to the MCU.
- Block (15): Radio SRAM
- Contains received packet data and instructions for transmit waveforms.
- Also contains data for data recovery circuit on how long of a packet to expect at a given time.
- Is shared between TX Gen. and Data Recovery blocks.
- Block (16): FPGA FSM
- A small finite state machine that manages movements into and out of the mode in which the Radio FSM controls the S.U.R.F.E.R. RFID radio.
- Block (7): SPI Controller
- An onboard SPI controller which drives the SX1257 radio IC and the digitally tunable capacitors.
- This controller is driven by the TX cancel block or the MCU through the SPI pass-thru.
- Block (8): SPI Pass-Thru
- Not a real block, more of an abstraction.
- This feature permits the MCU SPI to access the SX1257 radio IC SPI interface.
- Block (9): SPI Peripheral
- The main control interface of the FPGA as seen by the MCU.
- The MCU writes to different registers in the FPGA using this interface to effect various state changes in the FPGA.
When arranged in a hierarchical fashion, the files found in the FPGA repository can be considered as in the diagram to the right. Some of these files correspond exactly to the blocks shown in the top-level diagram at the top of these page. These files are numbered with the same numbers of their corresponding block in the top-level diagram. Some of the smaller files at the leaves of the tree are simple functions that were broken out into their own file to either control or more easily visualize their FPGA resource usage.
- rfidr_top_e144_c8g.v(1): Top Level.
- rxchain.v: Encapsulates (2)(3)(4).
- cic_8.v(2): Cascaded integrator-comb filter and decimation by 8, as described above.
- dec_128.v(3): Very low pass filter and decimation by 128, as described above.
- chnl_filt.v(4): Channel filter, as described above.
- chnl_filt_dfii.v: A direct-form II implementation of a second-order resonator for the channel filter.
- chnl_filt_dfii_onemult.v: A direct-form II implementation of the other second-order resonator for the channel filter.
- cdr_top.v(5): Clock and data recovery, as described above.
- clk_rcvy.v: A PLL-based clock and data recovery circuit.
- cr_phase_det.v: The phase detector of the clock recovery circuit.
- cr_period_sdm.v: The sigma-delta-based period dithering circuit of the clock recovery system.
- cr_freq_det.v: The frequency detector of the clock recovery circuit.
- data_rcvy.v: The data recovery circuit, as described above.
- crc_ccitt16_rx.v: The 16-bit CRC check for received tag responses.
- data_recovery_readout_ram.qip: To save LUT that would go to a giant mux tree, recovered data is pushed to an SRAM.
- flip_mux_main_lut.v: A signal inverter for the main amplitude integrator of the data recovery circuit. File name is a historical misnomer.
- flip_mux_alt.v: A signal inverter for the alternate amplitude integrator of the data recovery circuit. File name is a historical misnomer.
- swap_mux.v: A combination signal inverter and multiplexer for the input of the data recovery circuit. Probably should have been called "flip mux".
- thresh_slope_comparisons.v: Contains amplitude comparisons relevant for signal acquisition at the beginning of the tag response.
- timer_comparisons.v: Contains time comparisons relevant for signal acquisition at the beginning of the tag response.
- rn16_and_handle_shift_regs.v: Stores tag RN16 and handle from data recovery for use in tx_gen.v.
- txcancel.v(6): Transmit leakage cancellation algorithm, as described above.
- dtc_state_saturate.v: Saturates the DTC state values between 0 and 1023 so that they don't roll over.
- txcancel_mem.qip: Was for old nonblind transmit leakage algorithm. Is no longer used.
- spi.v: Encapsulates (7)(8)(9) above.
- spi_cntrlr.v(7,8): SPI Controller, as described above.
- spi_prphrl.v(8,9): SPI Peripheral, as described above.
- tx_gen.v(10): Transmit baseband waveform generator, as described above.
- tx_sdm_c8g.v(11): Transmit sigma-delta modulator to interface with SX1257 DAC. Also compensates for SX1257 DAC I offset.
- tx_zero_pattern_gen_c8g.v(12): Generates a "zero" waveform with a pattern with impulses at nulls of DAC filter. Also compensates for SX1257 DAC Q offset.
- clk_and_reset_mgmt.v(13): Clock and reset management, as described above.
- clk_mgmt.v: Clock buffers, dividers, and clock check circuits.
- clk_gate_buf.qsys: Dedicated clock buffer onboard the 10M02 FPGA.
- clk_mgmt_div_by_8.v: Generates 4.5MHz clock from 36MHz clock. Also provides sync signal for CIC decimation.
- internal_osc.qsys: Internal FPGA oscillator, source of 27.5MHz clock.
- reset_mgmt.v: Asynchronous reset deassert retiming.
- clk_crossings.v: Dual-flip-flop clock domain crossings.
- irq_merge.v: Simple block to merge all of the interrupt sources to flow to the interrupt assert pin.
- radio_fsm.v(14): Radio finite state machine to control UHF RFID time-critical radio operations, as described above.
- radio_sram_with_mux.v(15): SRAM that is muxed between tx_gen.v and data_rcvy.v, as described above.
- radio_sram.qip: The actual SRAM core of the SRAM with mux.
- rfidr_fsm.v(16): A simple finite machine state machine to control the FPGA. Probably should have been called fpga_fsm.v.
- wave_storage.v(17): Disabled. As described above, routes raw I/Q RX data into a huge SRAM for advanced localization.
- wave_storage_ram.qip(18): Disabled. As described above, is a huge SRAM for storing waveform data.