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CI: Bump riscv-gnu-toolchain #444

Merged
merged 3 commits into from
May 28, 2024
Merged

CI: Bump riscv-gnu-toolchain #444

merged 3 commits into from
May 28, 2024

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jserv
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@jserv jserv commented May 21, 2024

Nightly Release: April 12, 2024

@henrybear327
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We might also want to bump the reference device binary.

@visitorckw
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It's weird to see an error message from the assembler. This makes me wonder if it might be a compatibility issue or an error between the upstream toolchain and the riscv-arch-test?

@vacantron
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vacantron commented May 26, 2024

@jserv, I bump riscv-arch-test to ed32d67 also and the error is disappeared. Can you confirm this?

@visitorckw
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@jserv, I bump riscv-arch-test to ed32d67 also and the error is disappeared. Can you confirm this?

FWIW, it resolved the issue in my environment.

Tested-by: Kuan-Wei Chiu <visitorckw@gmail.com>

@visitorckw
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However, although it no longer encounters assembler errors and runs the compliance test correctly, it fails to pass the test suite for the M and A extensions. Additionally, in the C extension tests, it encounters the following assertion error:

rv32emu: src/emulate.c:650: block_translate: Assertion `prev_ir' failed.
Aborted (core dumped)

@jserv
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jserv commented May 27, 2024

We might also want to bump the reference device binary.

@vacantron, can you rebuild tests/arch-test-target/sail_cSim/riscv_sim_RV32 based on the latest riscv-arch-test and resolve the potential compliance issues? You can simply update arch-test branch, so that I can cherry-pick git commits.

@vacantron
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However, although it no longer encounters assembler errors and runs the compliance test correctly, it fails to pass the test suite for the M and A extensions. Additionally, in the C extension tests, it encounters the following assertion error:

rv32emu: src/emulate.c:650: block_translate: Assertion `prev_ir' failed.
Aborted (core dumped)

AFAIK, this error might happen when configuring the rv32emu with ENABLE_JIT=1 ENABLE_EXT_M=0. Can you provide more detailed testing steps?

@visitorckw
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AFAIK, this error might happen when configuring the rv32emu with ENABLE_JIT=1 ENABLE_EXT_M=0. Can you provide more detailed testing steps?

Ah, I must have forgotten to run make clean to remove the previously compiled test executable, which caused the aforementioned error. After retesting, everything seems to be normal. Thanks.

@vacantron
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We might also want to bump the reference device binary.

@vacantron, can you rebuild tests/arch-test-target/sail_cSim/riscv_sim_RV32 based on the latest riscv-arch-test and resolve the potential compliance issues? You can simply update arch-test branch, so that I can cherry-pick git commits.

Done in ecf6f1e.

@jserv jserv merged commit 88fa915 into master May 28, 2024
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@jserv jserv deleted the update-gnu-toolchain branch May 28, 2024 14:31
@jserv jserv added this to the release-2024.1 milestone Jun 4, 2024
henrybear327 added a commit to henrybear327/rv32emu that referenced this pull request Jun 16, 2024
henrybear327 added a commit to henrybear327/rv32emu that referenced this pull request Jun 16, 2024
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4 participants