correction for NI, and README

s4noc-chisel/Makefile

@@ -1,5 +1,5 @@
-PROJNAME = skeleton
-MAIN = skeleton.Skeleton
+PROJNAME = patmos
+MAIN = patmos.tNiBox
 MODULE ?= MAIN
 
 HWBUILDDIR ?= $(CURDIR)/hwbuild

s4noc-chisel/README.md

@@ -1,3 +1,11 @@
 # s4NOC
 
-s4noc chisel implementation
+An attempt to create a similar to s4noc chisel implementation
+It requires connections between the different elements.
+
+The main file to run is patmos.tNiBox.
+
+schnirom*.scala Small rom files created however, they are not scalable 
+and shall be replaced with one file which is configured and read in scala. 
+
+

s4noc-chisel/README.md~

@@ -0,0 +1,12 @@
+# s4NOC
+
+similar to s4noc chisel implementation
+
+The main file to run is patmos.tNiBox.
+
+It requires work on fixing the connections between the different element.
+
+schnirom*.scala Small rom files created however, they are not scalable 
+and shall be replaced with one file which is configured and read in scala. 
+
+

s4noc-chisel/chisel/RouterBox.scala

@@ -36,9 +36,17 @@ poke(dut.io.r_din.data,5)
 poke(dut.io.le_din.data,6)
 poke(dut.io.lc_din.data,7)
 
-//expect(dut.io.up_dout.data,3)
+
 step(1)
 
+peek(dut.io.up_dout.data)
+peek(dut.io.dn_dout.data)
+peek(dut.io.r_dout.data)
+peek(dut.io.le_dout.data)
+peek(dut.io.lc_dout.data)
+
+step(50)
+
 }
 
 object tRouterBox {

s4noc-chisel/chisel/Skeleton.scala

@@ -1 +1 @@
-package patmos
+package skeleton

s4noc-chisel/chisel/connectionsN.scala

@@ -108,6 +108,7 @@ class ipNI() extends Bundle(){
   val ip_ack = Bool(OUTPUT)
   val ip_addr = Bits(INPUT, ADDRESS_WIDTH)
   val ip_qtBusy = Bool(OUTPUT)
+  val ip_qrBusy= Bool(OUTPUT)
   val ip_dout = Bits(OUTPUT, DATA_WIDTH)
 
 }

s4noc-chisel/chisel/ip.scala

@@ -9,6 +9,7 @@ class Ip() extends Module {
 
       io.ipNI_io.ip_din:= Bits(0)
       io.ipNI_io.ip_addr:= Bits(0)
+      io.ipNI_io.ip_rtw:= Bool(true)
       io.led1:=UInt(0) 
       io.led2:= UInt(0)
 
@@ -28,7 +29,7 @@ class Ip() extends Module {
     when (transmit){
       io.ipNI_io.ip_din:= TEST_VALUE_1
       io.ipNI_io.router_tx:= Bool(true) 
-      io.ipNI_io.ip_addr:= Bits(10) // suppose to change
+      io.ipNI_io.ip_addr:= Bits(5) // suppose to change
     }
   }
 //  io.led1 := blkReg
@@ -68,4 +69,4 @@ object tIpBox {
 
 
 
-
+

s4noc-chisel/chisel/ni.scala

@@ -34,4 +34,4 @@ import ConstantsN._
 //         dut => new niTest(dut)
 //       }
 //   }
-// }
+// }

s4noc-chisel/chisel/niBox.scala

@@ -54,104 +54,128 @@ for (i <- 0 until TOTAL_IP_NUM) {
 }
 //niControllers(0).io <> rom0 
 
-
+*/
  // ================================================
  //  Create routers
  // ================================================
-val routers = for() yield{
-
+val routers = for(i<- 0 until TOTAL_IP_NUM) yield{
+  val rC = Module(new RouterBox())
+	rC
 }
 
-*/
  // ================================================
- //  Connections
+ //  Connections niCOntroller to ROMs
  // ================================================
 
+niControllers(0).io.dir_rdAddr <> rom0.io.dir.rdAddr
+niControllers(0).io.dir_rdData_src <> rom0.io.dir.rdData.src
+niControllers(0).io.dir_rdData_dst <> rom0.io.dir.rdData.dst
+niControllers(0).io.dir_read <> rom0.io.dir.read
 
+niControllers(1).io.dir_rdAddr <> rom1.io.dir.rdAddr
+niControllers(1).io.dir_rdData_src <> rom1.io.dir.rdData.src
+niControllers(1).io.dir_rdData_dst <> rom1.io.dir.rdData.dst
+niControllers(1).io.dir_read <> rom1.io.dir.read
 
+niControllers(2).io.dir_rdAddr <> rom2.io.dir.rdAddr
+niControllers(2).io.dir_rdData_src <> rom2.io.dir.rdData.src
+niControllers(2).io.dir_rdData_dst <> rom2.io.dir.rdData.dst
+niControllers(2).io.dir_read <> rom2.io.dir.read
 
-//schedule_ni.io.dir.rdAddr <>control_ni.io.dir_rdAddr
-//schedule_ni.io.dir.rdData.src <> control_ni.io.dir_rdData_src
+niControllers(3).io.dir_rdAddr <> rom3.io.dir.rdAddr
+niControllers(3).io.dir_rdData_src <> rom3.io.dir.rdData.src
+niControllers(3).io.dir_rdData_dst <> rom3.io.dir.rdData.dst
+niControllers(3).io.dir_read <> rom3.io.dir.read
 
-//schedule_ni.io.dir.rdData.dst <> control_ni.io.dir_rdData_dst
-//schedule_ni.io.dir.read <> control_ni.io.dir_read
+niControllers(4).io.dir_rdAddr <> rom4.io.dir.rdAddr
+niControllers(4).io.dir_rdData_src <> rom4.io.dir.rdData.src
+niControllers(4).io.dir_rdData_dst <> rom4.io.dir.rdData.dst
+niControllers(4).io.dir_read <> rom4.io.dir.read
 
-//io.core_io <> control_ni.io.ipNI_io
-//control_ni.io.r_lc_dout <> io.output1
+niControllers(5).io.dir_rdAddr <> rom5.io.dir.rdAddr
+niControllers(5).io.dir_rdData_src <> rom5.io.dir.rdData.src
+niControllers(5).io.dir_rdData_dst <> rom5.io.dir.rdData.dst
+niControllers(5).io.dir_read <> rom5.io.dir.read
 
-}
+niControllers(6).io.dir_rdAddr <> rom6.io.dir.rdAddr
+niControllers(6).io.dir_rdData_src <> rom6.io.dir.rdData.src
+niControllers(6).io.dir_rdData_dst <> rom6.io.dir.rdData.dst
+niControllers(6).io.dir_read <> rom6.io.dir.read
 
+niControllers(7).io.dir_rdAddr <> rom7.io.dir.rdAddr
+niControllers(7).io.dir_rdData_src <> rom7.io.dir.rdData.src
+niControllers(7).io.dir_rdData_dst <> rom7.io.dir.rdData.dst
+niControllers(7).io.dir_read <> rom7.io.dir.read
 
-class TestNiBox(dut: NiBox) extends Tester(dut) {
+niControllers(8).io.dir_rdAddr <> rom8.io.dir.rdAddr
+niControllers(8).io.dir_rdData_src <> rom8.io.dir.rdData.src
+niControllers(8).io.dir_rdData_dst <> rom8.io.dir.rdData.dst
+niControllers(8).io.dir_read <> rom8.io.dir.read
 
-     poke(dut.io.core_io.ip_rtw,1)
-     poke(dut.io.core_io.ip_din,15)
-     poke(dut.io.core_io.ip_addr,5)
-peek(dut.io.output1)
-   step(1)
-     poke(dut.io.core_io.ip_rtw,0)
-peek(dut.io.output1)
-  step(1)
-    peek(dut.io.output1)
-  step(1)  
-  peek(dut.io.output1)
-  step(1)
-  peek(dut.io.output1)
-  step(1)
+niControllers(9).io.dir_rdAddr <> rom9.io.dir.rdAddr
+niControllers(9).io.dir_rdData_src <> rom9.io.dir.rdData.src
+niControllers(9).io.dir_rdData_dst <> rom9.io.dir.rdData.dst
+niControllers(9).io.dir_read <> rom9.io.dir.read
 
-peek(dut.io.output1)
-  step(1)
+niControllers(10).io.dir_rdAddr <> rom10.io.dir.rdAddr
+niControllers(10).io.dir_rdData_src <> rom10.io.dir.rdData.src
+niControllers(10).io.dir_rdData_dst <> rom10.io.dir.rdData.dst
+niControllers(10).io.dir_read <> rom10.io.dir.read
 
-peek(dut.io.output1)
-  step(1)
 
-peek(dut.io.output1)
-  step(1)
+niControllers(11).io.dir_rdAddr <> rom11.io.dir.rdAddr
+niControllers(11).io.dir_rdData_src <> rom11.io.dir.rdData.src
+niControllers(11).io.dir_rdData_dst <> rom11.io.dir.rdData.dst
+niControllers(11).io.dir_read <> rom11.io.dir.read
 
-peek(dut.io.output1)
-  step(1)
+niControllers(12).io.dir_rdAddr <> rom12.io.dir.rdAddr
+niControllers(12).io.dir_rdData_src <> rom12.io.dir.rdData.src
+niControllers(12).io.dir_rdData_dst <> rom12.io.dir.rdData.dst
+niControllers(12).io.dir_read <> rom12.io.dir.read
 
-peek(dut.io.output1)
-  step(1)
 
-peek(dut.io.output1)
-  step(1)
+niControllers(13).io.dir_rdAddr <> rom13.io.dir.rdAddr
+niControllers(13).io.dir_rdData_src <> rom13.io.dir.rdData.src
+niControllers(13).io.dir_rdData_dst <> rom13.io.dir.rdData.dst
+niControllers(13).io.dir_read <> rom13.io.dir.read
 
-peek(dut.io.output1)
-  step(1)
 
-peek(dut.io.output1)
-  step(1)
+niControllers(14).io.dir_rdAddr <> rom14.io.dir.rdAddr
+niControllers(14).io.dir_rdData_src <> rom14.io.dir.rdData.src
+niControllers(14).io.dir_rdData_dst <> rom14.io.dir.rdData.dst
+niControllers(14).io.dir_read <> rom14.io.dir.read
 
-peek(dut.io.output1)
-  step(1)
 
-peek(dut.io.output1)
-  step(1)
+niControllers(15).io.dir_rdAddr <> rom15.io.dir.rdAddr
+niControllers(15).io.dir_rdData_src <> rom15.io.dir.rdData.src
+niControllers(15).io.dir_rdData_dst <> rom15.io.dir.rdData.dst
+niControllers(15).io.dir_read <> rom15.io.dir.read
 
-peek(dut.io.output1)
-  step(1)
+// each ipCore must connect to each ni_controller
+/*
+for (i<-0 until TOTAL_IP_NUM){
+  ipCores(i).io.ipNI_io <> niControllers(i).io.ipNI_io
+}*/
 
-peek(dut.io.output1)
-  step(1)
+// ======
+// connecting one core inputs on niController(0) for testing
+// ======
+niControllers(0).io.r_lc_dout <> io.output1
+io.core_io <> niControllers(0).io.ipNI_io
 
-peek(dut.io.output1)
-  step(1)
+}
 
-peek(dut.io.output1)
-  step(1)
 
-peek(dut.io.output1)
-  step(1)
+class TestNiBox(dut: NiBox) extends Tester(dut) {
 
+     poke(dut.io.core_io.ip_rtw,1)
+     poke(dut.io.core_io.ip_din,15)
+     poke(dut.io.core_io.ip_addr,14)
 peek(dut.io.output1)
-  step(1)
-
+   step(1)
+     poke(dut.io.core_io.ip_rtw,0)
 peek(dut.io.output1)
-  step(1)
-
-//expect(dut.io.up_dout.data,3)
-step(1)
+step(50)
 
 }
 

s4noc-chisel/chisel/niQueue.scala

@@ -75,7 +75,6 @@ class niQueue(length: Int) extends Module {
 
   val qt = Vec.fill(length) { Reg(init = qphit_init_state) }
 
-//  val qReceived = Vec.fill(length) { Reg(init = qphit_init_state) }
 
 // =====================================================================
 // Insert Element in TransmitQueue
@@ -111,6 +110,51 @@ class niQueue(length: Int) extends Module {
     qtPhitCount := qtPhitCount - UInt(1)
   }
 
+
+// =====================================================================
+// qr: Queue Receive
+// =====================================================================
+
+  val qrHead = Reg(init = UInt(0, width = log2Up(length)))
+  val qrTail = Reg(init = UInt(0, width = log2Up(length)))
+
+  val qrPhitCount = Reg(init = UInt(0, width = log2Up(length+1)))
+
+  val qrInc = Bool() 
+      qrInc := Bool(false)
+  val qrDec = Bool()
+      qrDec := Bool(false)
+
+  val qrFull = Bool()
+      qrFull:= (qrPhitCount === UInt(length))
+
+  val qrEmpty = Bool()
+      qrEmpty:=(qrPhitCount === UInt(0))
+
+  val qrTailNext = UInt(width = log2Up(length))
+      qrTailNext := Mux(qrTail === UInt(length), UInt(0), qrTail + UInt(1))
+
+  val qrHeadNext = UInt(width = log2Up(length))
+      qrHeadNext := Mux(qrHead === UInt(length), UInt(0), qrHead + UInt(1))
+// =====================================================================
+// qr: Signal state of Queueu Receive
+// =====================================================================
+  io.ipNI_io.ip_qrBusy:= qrFull
+// =====================================================================
+// Inistantiate phit - queue elements
+// =====================================================================
+
+  val qr = Vec.fill(length) { Reg(init = qphit_init_state) }
+
+// =====================================================================
+// Insert Element in ReceiveQueue
+// =====================================================================
+
+
+// =====================================================================
+// Remove Element in ReceiveQueue
+// =====================================================================
+
 
 // =======================================
 //    NI - SCHEDULE 
@@ -189,23 +233,7 @@ when (reg_dir_data_dst === reg_tx_dst){
     peek(dut.tx_dout)
      expect(dut.qtPhitCount,2)
      expect(dut.io.ipNI_io.ip_qtBusy,0)
-   step(1)
-
-     poke(dut.io.ipNI_io.ip_addr,3)
-     expect(dut.qtPhitCount,2)
-
-    peek(dut.io.r_lc_dout)
-    peek(dut.tx_dout)
-     expect(dut.io.ipNI_io.ip_qtBusy,0)
-   step(1)
-
-     expect(dut.qtPhitCount,2)
-     expect(dut.io.ipNI_io.ip_qtBusy,0)
-   step(1)
-
-     expect(dut.qtPhitCount,2)
-     expect(dut.io.ipNI_io.ip_qtBusy,0)
-   step(1)
+   step(100)
 
 }