The way of changing the network size has been updated, now it can be …

…done only by modifying the generic_noc_types.vhd.

Makefile

@@ -33,6 +33,7 @@ update_leros:
 
 tools:
 	cd leros && make tools
+	cd noc && make tools
 
 compile:
 #	cd leros/LerosMuviumSDK && makeTest.bat

noc/Makefile

@@ -27,6 +27,8 @@ base: leros
 	$(WINE) vcom $(OPTIONS) $(S4NOCDIR)/serdes.vhd
 	$(WINE) vcom $(OPTIONS) $(S4NOCDIR)/generated/bt$(N)x$(N)/router_ST.vhd
 	$(WINE) vcom $(OPTIONS) $(S4NOCDIR)/generated/bt$(N)x$(N)/ni_ST.vhd
+	$(WINE) vsom $(OPTIONS) $(S4NOCDIR)/router_ST.vhd
+	$(WINE) vsom $(OPTIONS) $(S4NOCDIR)/ni_ST.vhd
 	$(WINE) vcom $(OPTIONS) $(S4NOCDIR)/dp_ram.vhd
 	$(WINE) vcom $(OPTIONS) $(S4NOCDIR)/ni_ram.vhd
 	$(WINE) vcom $(OPTIONS) $(S4NOCDIR)/ni_ram_single.vhd
@@ -48,6 +50,20 @@ leros:
 	$(WINE) vcom $(OPTIONS) $(LEROSDIR)/core/leros_ex.vhd
 	$(WINE) vcom $(OPTIONS) $(LEROSDIR)/core/leros.vhd
 
+tools:
+	cd src && make
+
+schedule:
+	cd vhdl/generated/bt2x2 && ../../../src/STgen.exe 4 bt2x2.shd
+	cd vhdl/generated/bt3x3 && ../../../src/STgen.exe 9 bt3x3.shd
+	cd vhdl/generated/bt4x4 && ../../../src/STgen.exe 16 bt4x4.shd
+	cd vhdl/generated/bt5x5 && ../../../src/STgen.exe 25 bt5x5.shd
+	cd vhdl/generated/bt6x6 && ../../../src/STgen.exe 36 bt6x6.shd
+	cd vhdl/generated/bt7x7 && ../../../src/STgen.exe 49 bt7x7.shd
+	cd vhdl/generated/bt8x8 && ../../../src/STgen.exe 64 bt8x8.shd
+	cd vhdl/generated/bt9x9 && ../../../src/STgen.exe 81 bt9x9.shd
+	cd vhdl/generated/bt10x10 && ../../../src/STgen.exe 100 bt10x10.shd
+
 sim: 
 	@echo Starting simulation...
 	$(WINE) vcom $(OPTIONS) $(S4NOCDIR)/simulation/tb_noc.vhd

noc/quartus/tile_test_alt/tile_test_alt.qsf

@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP2C70F896C6
 set_global_assignment -name TOP_LEVEL_ENTITY tile_test_alt
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:54:00  MARCH 23, 2012"
-set_global_assignment -name LAST_QUARTUS_VERSION 11.1
+set_global_assignment -name LAST_QUARTUS_VERSION 12.0
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
@@ -63,10 +63,24 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES OFF
+set_global_assignment -name VHDL_FILE ../../vhdl/ni_ST.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt8x8/router_ST_64.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt8x8/ni_ST_64.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt7x7/router_ST_49.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt7x7/ni_ST_49.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt6x6/router_ST_36.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt6x6/ni_ST_36.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt5x5/router_ST_25.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt5x5/ni_ST_25.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt3x3/router_ST_9.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt3x3/ni_ST_9.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt4x4/router_ST_16.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt4x4/ni_ST_16.vhd
+set_global_assignment -name VHDL_FILE ../../vhdl/router_ST.vhd
 set_global_assignment -name VHDL_FILE ../../vhdl/ni_ram_single.vhd
 set_global_assignment -name VHDL_FILE ../../vhdl/generic_noc_types.vhd
-set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt4x4/router_ST.vhd
-set_global_assignment -name VHDL_FILE ../../vhdl/generated/bt4x4/ni_ST.vhd
 set_global_assignment -name VHDL_FILE ../../vhdl/tile_top.vhd
 set_global_assignment -name VHDL_FILE ../../../leros/vhdl/generated/leros_rom.vhd
 set_global_assignment -name VHDL_FILE ../../../leros/vhdl/io/uart.vhd
@@ -86,6 +100,4 @@ set_global_assignment -name VHDL_FILE ../../vhdl/noc_N.vhd
 set_global_assignment -name VHDL_FILE ../../vhdl/ni_ram.vhd -hdl_version VHDL_2008
 set_global_assignment -name VHDL_FILE ../../vhdl/dp_ram.vhd
 set_global_assignment -name SIGNALTAP_FILE stp1.stp
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
-set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES OFF
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

noc/src/STgen.cpp

@@ -35,7 +35,7 @@ int main(int argc,char *argv[]){
 	string token;
 	port inputPort = L;
 	int startTime = 0;
-	STprint* printer = new STprint();
+	STprint* printer = new STprint(numOfNodes);
 
 	cout << "Shd file:\t" << inputPath << endl;
 

noc/src/STprint.cpp

@@ -37,6 +37,10 @@ class STprint{
 	ofstream niST;
 	ofstream routerST;
 
+	char niST_name[20];
+	char routerST_name[20];
+	const int numOfNodes;
+
 	string bin(int val, int bits) {
 	int max = (int)pow(2.0,bits-1);
 	string s = "";
@@ -54,9 +58,11 @@ class STprint{
 
 public:
 
-	STprint(){
-		niST.open("ni_ST.vhd", ios::trunc);
-		routerST.open("router_ST.vhd", ios::trunc);
+	STprint(int _numOfNodes): numOfNodes(_numOfNodes){
+		sprintf(niST_name,"ni_ST_%i.vhd",numOfNodes);
+		sprintf(routerST_name,"router_ST_%i.vhd",numOfNodes);
+		niST.open(niST_name, ios::trunc);
+		routerST.open(routerST_name, ios::trunc);
 	}
 
 	~STprint(){
@@ -78,24 +84,26 @@ class STprint{
 
 	void writeHeaderRouter(int countWidth){
 		routerST << "-------------------------------------------------------------\n";
-		routerST << "-- router_ST.vhd\n";
+		routerST << "-- " << routerST_name << "\n";
 		routerST << "-- This is an auto generated file, do not edit by hand.\n";
 		routerST << "-------------------------------------------------------------\n";
 		routerST << "library ieee;\n";
 		routerST << "use ieee.std_logic_1164.all;\n";
 		routerST << "use ieee.numeric_std.all;\n\n";
 
-		routerST << "use work.leros_types.all;\n";
 		routerST << "use work.noc_types.all;\n\n";
 
-		routerST << "entity router_ST is\n";
+		routerST << "entity router_ST_" << numOfNodes << " is\n";
+		routerST << "\tgeneric (\n";
+		routerST << "\t\tNI_NUM\t: natural\n";
+		routerST << "\t\t);\n";
 		routerST << "\tport (\n";
 		routerST << "\t\tcount\t: in unsigned(" << countWidth-1 << " downto 0);\n";
 		routerST << "\t\tsels\t: out select_signals\n";
 		routerST << "\t\t);\n";
 
-		routerST << "end router_ST;\n\n";
-		routerST << "architecture data of router_ST is\n";
+		routerST << "end router_ST_" << numOfNodes << ";\n\n";
+		routerST << "architecture data of router_ST_" << numOfNodes << " is\n";
 		routerST << "begin -- data\n\n";
 		routerST << "process(count) begin\n\n";
 		routerST << "\tcase count is\n\n";
@@ -120,17 +128,16 @@ class STprint{
 
 	void writeHeaderNI(int countWidth, int numOfNodes){
 		niST << "-------------------------------------------------------------\n";
-		niST << "-- ni_ST.vhd\n";
+		niST << "-- " << niST_name << "\n";
 		niST << "-- This is an auto generated file, do not edit by hand.\n";
 		niST << "-------------------------------------------------------------\n";
 		niST << "library ieee;\n";
 		niST << "use ieee.std_logic_1164.all;\n";
 		niST << "use ieee.numeric_std.all;\n\n";
 
-		niST << "use work.leros_types.all;\n";
 		niST << "use work.noc_types.all;\n\n";
 
-		niST << "entity ni_ST is\n";
+		niST << "entity ni_ST_" << numOfNodes << " is\n";
 		niST << "\tgeneric (\n";
 		niST << "\t\tNI_NUM\t: natural);\n";
 		niST << "\tport (\n";
@@ -139,8 +146,8 @@ class STprint{
 		niST << "\t\tsrc\t: out integer range 0 to " << numOfNodes-1 << "\n";
 		niST << "\t\t);\n";
 
-		niST << "end ni_ST;\n\n";
-		niST << "architecture data of ni_ST is\n";
+		niST << "end ni_ST_" << numOfNodes << ";\n\n";
+		niST << "architecture data of ni_ST_" << numOfNodes << " is\n";
 		niST << "begin -- data\n\n";
 
 	}