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Update ip-contributions version
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schoeberl committed Nov 17, 2022
1 parent 2cd0295 commit 6d567b1
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Showing 2 changed files with 4 additions and 14 deletions.
8 changes: 4 additions & 4 deletions build.sbt
Original file line number Diff line number Diff line change
Expand Up @@ -7,19 +7,19 @@ scalacOptions ++= Seq(
"-language:reflectiveCalls",
)

val chiselVersion = "3.5.3"
val chiselVersion = "3.5.5"
addCompilerPlugin("edu.berkeley.cs" %% "chisel3-plugin" % chiselVersion cross CrossVersion.full)
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % chiselVersion
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.3"
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.5"

// For FIFO buffers
libraryDependencies += "edu.berkeley.cs" % "ip-contributions" % "0.5.0"
libraryDependencies += "edu.berkeley.cs" % "ip-contributions" % "0.5.1"

// library name
name := "soc-comm"

// library version
version := "0.1.2"
version := "0.1.3"

// groupId, SCM, license information
organization := "io.github.t-crest"
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10 changes: 0 additions & 10 deletions src/test/scala/s4noc/NocTest.scala
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,6 @@ class NocTest extends AnyFlatSpec with ChiselScalatestTester {
if (helpRcv.rxAvail) {
assert(helpRcv.receive == BigInt("cafebabe", 16))
assert(helpRcv.getSender() == 0)
// println("Got a packet")
done = true
}
}
Expand All @@ -48,7 +47,6 @@ class NocTest extends AnyFlatSpec with ChiselScalatestTester {
}
}

/*
it should "have the correct sender ID in the IO register" in {
val n = 4
test(new S4NoCTop(Config(n, 16, 2, 2, 32))) { d =>
Expand All @@ -71,10 +69,7 @@ class NocTest extends AnyFlatSpec with ChiselScalatestTester {
}
}

*/


/*
it should "have the correct sender ID in the IO register, multi threaded" in {
val n = 4
test(new S4NoCTop(Config(n, 16, 2, 2, 32))).withAnnotations(Seq(WriteVcdAnnotation)) { d =>
Expand All @@ -92,9 +87,6 @@ class NocTest extends AnyFlatSpec with ChiselScalatestTester {
println(s"send from $i to $j")
}
}
// help(i).step(50)
// TODO: when the rx FIFO is a memory (also register) FIFO this is broken
// TODO: probably enq and deq in same clock cycle bug
for (j <- 0 until n - 1) {
val data = help(i).receive
val from = help(i).getSender()
Expand All @@ -108,6 +100,4 @@ class NocTest extends AnyFlatSpec with ChiselScalatestTester {
}
}
}
*/
}

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