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Add complex128 support #2261

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Add complex128 support #2261

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f475574
Added complex128 support
hunkim May 7, 2016
e98bfca
Added complex128 support
hunkim May 7, 2016
c019c99
REGISTER+ and added REGISTER12
hunkim May 7, 2016
c1f2ff4
Added complex128 support
hunkim May 7, 2016
75f1270
Added complex128 support
hunkim May 7, 2016
bd79923
Added complex128 support for imag and real
hunkim May 7, 2016
58d3394
Added complex128 support for conj
hunkim May 7, 2016
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_add.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER9(BinaryOp, CPU, "Add", functor::add, float, Eigen::half, double, int32,
int64, int8, int16, complex64, string);
REGISTER10(BinaryOp, CPU, "Add", functor::add, float, Eigen::half, double, int32,
int64, int8, int16, complex64, complex128, string);
#if GOOGLE_CUDA
REGISTER4(BinaryOp, GPU, "Add", functor::add, float, Eigen::half, double,
int64);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_conj.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER_KERNEL_BUILDER(Name("Conj").Device(DEVICE_CPU),
UnaryOp<CPUDevice, functor::conj<complex64>>);
REGISTER2(UnaryOp, CPU, "Conj", functor::conj, complex64, complex128);

#if GOOGLE_CUDA
// REGISTER_KERNEL_BUILDER(Name("Conj").Device(DEVICE_GPU),
// UnaryOp<GPUDevice, functor::conj<complex64>>);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_cos.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Cos", functor::cos, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Cos", functor::cos, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Cos", functor::cos, float, Eigen::half, double);
#endif
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_div.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(BinaryOp, CPU, "Div", functor::div, float, Eigen::half, double,
complex64);
REGISTER5(BinaryOp, CPU, "Div", functor::div, float, Eigen::half, double,
complex64, complex128);
REGISTER4(BinaryOp, CPU, "Div", functor::safe_div, uint8, int16, int32, int64);
#if GOOGLE_CUDA
REGISTER6(BinaryOp, GPU, "Div", functor::div, float, Eigen::half, double, uint8,
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_equal_to.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER11(BinaryOp, CPU, "Equal", functor::equal_to, float, Eigen::half,
double, uint8, int8, int16, int32, int64, complex64, string, bool);
REGISTER12(BinaryOp, CPU, "Equal", functor::equal_to, float, Eigen::half,
double, uint8, int8, int16, int32, int64, complex64, complex128, string, bool);
#if GOOGLE_CUDA
REGISTER8(BinaryOp, GPU, "Equal", functor::equal_to, float, Eigen::half, double,
uint8, int8, int16, int64, bool);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_exp.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Exp", functor::exp, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Exp", functor::exp, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Exp", functor::exp, float, Eigen::half, double);
#endif
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2 changes: 1 addition & 1 deletion tensorflow/core/kernels/cwise_op_gpu_equal_to.cu.cc
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Expand Up @@ -20,7 +20,7 @@ limitations under the License.
namespace tensorflow {
namespace functor {
DEFINE_BINARY9(equal_to, float, Eigen::half, double, uint8, int8, int16, int64,
complex64, bool);
complex64, complex128, bool);
} // namespace functor
} // namespace tensorflow

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2 changes: 1 addition & 1 deletion tensorflow/core/kernels/cwise_op_gpu_imag.cu.cc
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Expand Up @@ -19,7 +19,7 @@ limitations under the License.

namespace tensorflow {
namespace functor {
DEFINE_UNARY1(get_imag, complex64);
DEFINE_UNARY2(get_imag, complex64, complex128);
} // namespace functor
} // namespace tensorflow

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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_gpu_not_equal_to.cu.cc
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Expand Up @@ -19,8 +19,8 @@ limitations under the License.

namespace tensorflow {
namespace functor {
DEFINE_BINARY9(not_equal_to, float, Eigen::half, double, uint8, int8, int16,
int64, complex64, bool);
DEFINE_BINARY10(not_equal_to, float, Eigen::half, double, uint8, int8, int16,
int64, complex64, complex128, bool);
} // namespace functor
} // namespace tensorflow

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2 changes: 1 addition & 1 deletion tensorflow/core/kernels/cwise_op_gpu_real.cu.cc
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Expand Up @@ -19,7 +19,7 @@ limitations under the License.

namespace tensorflow {
namespace functor {
DEFINE_UNARY1(get_real, complex64);
DEFINE_UNARY2(get_real, complex64, complex128);
} // namespace functor
} // namespace tensorflow

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1 change: 1 addition & 0 deletions tensorflow/core/kernels/cwise_op_gpu_select.cu.cc
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Expand Up @@ -77,6 +77,7 @@ SELECT_FUNCTOR(double);
SELECT_FUNCTOR(int32);
SELECT_FUNCTOR(int64);
SELECT_FUNCTOR(complex64);
SELECT_FUNCTOR(complex6128);

#undef SELECT_FUNCTOR

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7 changes: 3 additions & 4 deletions tensorflow/core/kernels/cwise_op_imag.cc
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Expand Up @@ -16,10 +16,9 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER_KERNEL_BUILDER(Name("Imag").Device(DEVICE_CPU),
UnaryOp<CPUDevice, functor::get_imag<complex64>>);
REGISTER2(UnaryOp, CPU, "Imag", functor::get_imag, complex64, complex128);

#if GOOGLE_CUDA
REGISTER_KERNEL_BUILDER(Name("Imag").Device(DEVICE_GPU),
UnaryOp<GPUDevice, functor::get_imag<complex64>>);
REGISTER2(UnaryOp, GPU, "Imag", functor::get_imag, complex64, complex128);
#endif
} // namespace tensorflow
4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_inverse.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Inv", functor::inverse, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Inv", functor::inverse, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER4(UnaryOp, GPU, "Inv", functor::inverse, float, Eigen::half, double,
int64);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_log.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Log", functor::log, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Log", functor::log, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Log", functor::log, float, Eigen::half, double);
#endif
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_mul.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER9(BinaryOp, CPU, "Mul", functor::mul, float, Eigen::half, double, uint8,
int8, int16, int32, int64, complex64);
REGISTER10(BinaryOp, CPU, "Mul", functor::mul, float, Eigen::half, double, uint8,
int8, int16, int32, int64, complex64, complex128);
#if GOOGLE_CUDA
REGISTER7(BinaryOp, GPU, "Mul", functor::mul, float, Eigen::half, double, uint8,
int8, int16, int64);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_neg.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER6(UnaryOp, CPU, "Neg", functor::neg, float, Eigen::half, double, int32,
complex64, int64);
REGISTER7(UnaryOp, CPU, "Neg", functor::neg, float, Eigen::half, double, int32,
int64, complex64, complex128);
#if GOOGLE_CUDA
REGISTER4(UnaryOp, GPU, "Neg", functor::neg, float, Eigen::half, double, int64);

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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_not_equal_to.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER11(BinaryOp, CPU, "NotEqual", functor::not_equal_to, float, Eigen::half,
double, uint8, int8, int16, int32, int64, complex64, string, bool);
REGISTER12(BinaryOp, CPU, "NotEqual", functor::not_equal_to, float, Eigen::half,
double, uint8, int8, int16, int32, int64, complex64, complex128, string, bool);
#if GOOGLE_CUDA
REGISTER8(BinaryOp, GPU, "NotEqual", functor::not_equal_to, float, Eigen::half,
double, uint8, int8, int16, int64, bool);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_pow.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER6(BinaryOp, CPU, "Pow", functor::pow, float, Eigen::half, double, int32,
int64, complex64);
REGISTER7(BinaryOp, CPU, "Pow", functor::pow, float, Eigen::half, double, int32,
int64, complex64, complex128);
#if GOOGLE_CUDA
REGISTER4(BinaryOp, GPU, "Pow", functor::pow, float, Eigen::half, double,
int64);
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7 changes: 3 additions & 4 deletions tensorflow/core/kernels/cwise_op_real.cc
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Expand Up @@ -16,10 +16,9 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER_KERNEL_BUILDER(Name("Real").Device(DEVICE_CPU),
UnaryOp<CPUDevice, functor::get_real<complex64>>);
REGISTER2(UnaryOp, CPU, "Real", functor::get_real, complex64, complex128);

#if GOOGLE_CUDA
REGISTER_KERNEL_BUILDER(Name("Real").Device(DEVICE_GPU),
UnaryOp<GPUDevice, functor::get_real<complex64>>);
REGISTER2(UnaryOp, GPU, "Real", functor::get_real, complex64, complex128);
#endif
} // namespace tensorflow
4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_rsqrt.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Rsqrt", functor::rsqrt, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Rsqrt", functor::rsqrt, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Rsqrt", functor::rsqrt, float, Eigen::half, double);
#endif
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1 change: 1 addition & 0 deletions tensorflow/core/kernels/cwise_op_select.cc
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Expand Up @@ -133,6 +133,7 @@ REGISTER_SELECT_GPU(double);
REGISTER_SELECT_GPU(int32);
REGISTER_SELECT_GPU(int64);
REGISTER_SELECT_GPU(complex64);
REGISTER_SELECT_GPU(complex128);

#undef REGISTER_SELECT_GPU

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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_sigmoid.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Sigmoid", functor::sigmoid, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Sigmoid", functor::sigmoid, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Sigmoid", functor::sigmoid, float, Eigen::half,
double);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_sign.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER6(UnaryOp, CPU, "Sign", functor::sign, float, double, int32, int64,
complex64, Eigen::half);
REGISTER7(UnaryOp, CPU, "Sign", functor::sign, float, double, int32, int64,
complex64, complex128, Eigen::half);
#if GOOGLE_CUDA
REGISTER4(UnaryOp, GPU, "Sign", functor::sign, float, Eigen::half, double,
int64);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_sin.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Sin", functor::sin, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Sin", functor::sin, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Sin", functor::sin, float, Eigen::half, double);
#endif
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_sqrt.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Sqrt", functor::sqrt, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Sqrt", functor::sqrt, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Sqrt", functor::sqrt, float, Eigen::half, double);
#endif
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_square.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER6(UnaryOp, CPU, "Square", functor::square, float, Eigen::half, double,
int32, complex64, int64);
REGISTER7(UnaryOp, CPU, "Square", functor::square, float, Eigen::half, double,
int32, int64, complex64, complex128);
#if GOOGLE_CUDA
REGISTER4(UnaryOp, GPU, "Square", functor::square, float, Eigen::half, double,
int64);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_sub.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER6(BinaryOp, CPU, "Sub", functor::sub, float, Eigen::half, double, int32,
int64, complex64);
REGISTER7(BinaryOp, CPU, "Sub", functor::sub, float, Eigen::half, double, int32,
int64, complex64, complex128);
#if GOOGLE_CUDA
REGISTER4(BinaryOp, GPU, "Sub", functor::sub, float, Eigen::half, double,
int64);
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4 changes: 2 additions & 2 deletions tensorflow/core/kernels/cwise_op_tanh.cc
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Expand Up @@ -16,8 +16,8 @@ limitations under the License.
#include "tensorflow/core/kernels/cwise_ops_common.h"

namespace tensorflow {
REGISTER4(UnaryOp, CPU, "Tanh", functor::tanh, float, Eigen::half, double,
complex64);
REGISTER5(UnaryOp, CPU, "Tanh", functor::tanh, float, Eigen::half, double,
complex64, complex128);
#if GOOGLE_CUDA
REGISTER3(UnaryOp, GPU, "Tanh", functor::tanh, float, Eigen::half, double);
#endif
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5 changes: 5 additions & 0 deletions tensorflow/core/kernels/cwise_ops_common.h
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Expand Up @@ -386,6 +386,8 @@ struct UnaryFunctor<CPUDevice, Functor> {
REGISTER(OP, D, N, F, T0)
#define REGISTER11(OP, D, N, F, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10) \
REGISTER(OP, D, N, F, T0)
#define REGISTER12(OP, D, N, F, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11) \
REGISTER(OP, D, N, F, T0)
#else // !defined(__ANDROID_TYPES_SLIM__)
#define REGISTER2(OP, D, N, F, T0, T1) \
REGISTER(OP, D, N, F, T0) \
Expand Down Expand Up @@ -417,6 +419,9 @@ struct UnaryFunctor<CPUDevice, Functor> {
#define REGISTER11(OP, D, N, F, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10) \
REGISTER5(OP, D, N, F, T0, T1, T2, T3, T4) \
REGISTER6(OP, D, N, F, T5, T6, T7, T8, T9, T10)
#define REGISTER12(OP, D, N, F, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11) \
REGISTER6(OP, D, N, F, T0, T1, T2, T3, T4, T5) \
REGISTER6(OP, D, N, F, T6, T7, T8, T9, T10, T11)
#endif // defined(__ANDROID_TYPES_SLIM__)

} // end namespace tensorflow
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