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[ROCm] Enable ROCm support for "shape" ops #26753

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May 6, 2019
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[ROCm] Enable ROCm support for "shape" ops #26753

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26 changes: 13 additions & 13 deletions tensorflow/core/kernels/shape_ops.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,7 @@ REGISTER_KERNEL_BUILDER(Name("Shape")
ShapeOp<int64>);
#endif // TENSORFLOW_USE_SYCL

#if GOOGLE_CUDA
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
#define REGISTER_GPU_KERNEL(type) \
REGISTER_KERNEL_BUILDER(Name("Shape") \
.Device(DEVICE_GPU) \
Expand Down Expand Up @@ -106,7 +106,7 @@ REGISTER_KERNEL_BUILDER(Name("Shape")
.TypeConstraint<int64>("out_type"),
ShapeOp<int64>);

#endif // GOOGLE_CUDA
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM

// ShapeN ---------------------------------------
REGISTER_KERNEL_BUILDER(Name("ShapeN")
Expand All @@ -120,7 +120,7 @@ REGISTER_KERNEL_BUILDER(Name("ShapeN")
.TypeConstraint<int64>("out_type"),
ShapeNOp<int64>);

#if GOOGLE_CUDA
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
#define REGISTER_GPU_KERNEL(type) \
REGISTER_KERNEL_BUILDER(Name("ShapeN") \
.Device(DEVICE_GPU) \
Expand Down Expand Up @@ -156,7 +156,7 @@ REGISTER_KERNEL_BUILDER(Name("ShapeN")
.TypeConstraint<int32>("T")
.TypeConstraint<int64>("out_type"),
ShapeNOp<int64>);
#endif // GOOGLE_CUDA
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM

#ifdef TENSORFLOW_USE_SYCL
#define REGISTER_SYCL_KERNEL(type) \
Expand Down Expand Up @@ -222,7 +222,7 @@ REGISTER_KERNEL_BUILDER(Name("Rank")
RankOp);
#endif // TENSORFLOW_USE_SYCL

#if GOOGLE_CUDA
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
#define REGISTER_GPU_KERNEL(type) \
REGISTER_KERNEL_BUILDER(Name("Rank") \
.Device(DEVICE_GPU) \
Expand Down Expand Up @@ -250,7 +250,7 @@ REGISTER_KERNEL_BUILDER(Name("Rank")
.HostMemory("output"),
RankOp);

#endif // GOOGLE_CUDA
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM

// Size ------------------------------------------
REGISTER_KERNEL_BUILDER(Name("Size")
Expand All @@ -264,7 +264,7 @@ REGISTER_KERNEL_BUILDER(Name("Size")
.TypeConstraint<int64>("out_type"),
SizeOp<int64>);

#if GOOGLE_CUDA
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
#define REGISTER_GPU_KERNEL(type) \
REGISTER_KERNEL_BUILDER(Name("Size") \
.Device(DEVICE_GPU) \
Expand Down Expand Up @@ -301,7 +301,7 @@ REGISTER_KERNEL_BUILDER(Name("Size")
.HostMemory("output"),
SizeOp<int64>);

#endif // GOOGLE_CUDA
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM

#ifdef TENSORFLOW_USE_SYCL
#define REGISTER_SYCL_KERNEL(type) \
Expand Down Expand Up @@ -349,7 +349,7 @@ REGISTER_KERNEL_BUILDER(Name("ExpandDims")
.TypeConstraint<int64>("Tdim"),
ExpandDimsOp<int64>);

#if GOOGLE_CUDA
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
#define REGISTER_GPU_KERNEL(type) \
REGISTER_KERNEL_BUILDER(Name("ExpandDims") \
.Device(DEVICE_GPU) \
Expand Down Expand Up @@ -383,7 +383,7 @@ REGISTER_KERNEL_BUILDER(Name("ExpandDims")
.HostMemory("dim")
.HostMemory("output"),
ExpandDimsOp<int64>);
#endif // GOOGLE_CUDA
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM

#ifdef TENSORFLOW_USE_SYCL
#define REGISTER_SYCL_KERNEL(type) \
Expand Down Expand Up @@ -424,7 +424,7 @@ REGISTER_KERNEL_BUILDER(Name("ExpandDims")
// Squeeze ---------------------------------------
REGISTER_KERNEL_BUILDER(Name("Squeeze").Device(DEVICE_CPU), SqueezeOp);

#if GOOGLE_CUDA
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
#define REGISTER_GPU_KERNEL(type) \
REGISTER_KERNEL_BUILDER( \
Name("Squeeze").Device(DEVICE_GPU).TypeConstraint<type>("T"), \
Expand All @@ -442,7 +442,7 @@ REGISTER_KERNEL_BUILDER(Name("Squeeze")
.HostMemory("input")
.HostMemory("output"),
SqueezeOp);
#endif // GOOGLE_CUDA
#endif // GOOGLE_CUDA || TENSORFLOW_USE_ROCM

#if TENSORFLOW_USE_SYCL
#define REGISTER_SYCL_KERNEL(type) \
Expand Down Expand Up @@ -532,7 +532,7 @@ REGISTER_GPU_KERNEL(Variant);

#undef REGISTER_GPU_KERNEL

#if GOOGLE_CUDA
#if GOOGLE_CUDA || TENSORFLOW_USE_ROCM
// A special GPU kernel for int32 and bool.
// TODO(b/25387198): Also enable int32 in device memory. This kernel
// registration requires all int32 inputs and outputs to be in host memory.
Expand Down