to_fpga_nativelink_simulation.rpt

Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cycloneive
Quartus root          :  d:/software/quartus_lite/quartus/bin64/
Quartus sim root      :  d:/software/quartus_lite/quartus/eda/sim_lib
Simulation Tool       :  questasim
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :  
Sim SDF file          :  
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with Questasim software
Sourced NativeLink script d:/software/quartus_lite/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File to_fpga_run_msim_rtl_verilog.do already exists - backing up current file as to_fpga_run_msim_rtl_verilog.do.bak11
Info: Spawning QuestaSim Simulation software 
Info: NativeLink simulation flow was successful