- This is a multi-core processor design for FPGA designed using SystemVerilog language.
- In this design
- Most of the important variables are parameterized. (Ex:- core-count of the multi-core processor, UART baudrate)
- Every core can access only the part of the memory allocated to it.
- Communication between laptop and FPGA happens using UART protocol.
- This is specially designed for matrix multiplication
- With current configurations, using single core upto 36x36 matrices can be multiplied.
- Top module (toFpga.sv) is designed for DE-115 Altera FPGA board. (To use for a different board, use appropriate input/outputs names in the top module)
- Simulation codes are given for most of the modules. (except for the time count display module)
- Questa-sim can be used for simulations.
- Set the "CORE_COUNT" in the toFpga.sv to set the number of cores in the multi-core proecessor.
- If requires to change the UART communication baud rate, set the "BAUD_RATE" in to_Fpga.sv and "baud_rate" in processor_matrix_multiplication.py. (Currently used value is 115200 for high speed transmission).
- Compile and upload to the DE2-115 board.
- Connect the RS-232 cable to the DE2-115. Make sure the "COM PORT" name is correct in functions.py
- Go to the "UART_INS" state by "KEY[1] push button.
- Run the processor_matrix_multiplication.py
- Set the matrix dimensions and number of cores in the multi-core processor.
- Wait few seconds for the data transmission and matrix multiplication.
- Clock counts for the multiplication is visible on the seven-segment display in decemal.
- Answer is verified within the laptop using a python function. (If there is an error it will be shown in the terminal.)
- All the data are saved in text files in the python_code_for_synthesis folder.
- By pressing KEY[0] in the FPGA board, the system go to the initial (ready) state. (System reset)
- Open Quartus Prime software and set the required module as Top-level Entity. (ex:- register.v)
- Do the Analysis & Elaboration.
- Go to Assignments -> Settings -> EDA Tool Settings -> Simulation
- Select the required test bench. (ex:- register_tb.v) and apply changes.
- Go to Tools -> Run Simulation -> RTL Simulation.
- Simulation will start in ModelSim or QuestaSim (as configured in Quartus Prime settings) then run untill the end and stop after at the end of the simulation.
- For the top level simulation simulation_top.sv and simulation_top_tb.sv are used.
- INS_RAM.sv and DATA_RAM.sv are only used for simulation for below mentioned modules. They are similar to the RAM.sv used for synthesis, but have simulation capabilities.
- Before simulate simulation_top_tb.sv, multi_core_processor_tb.sv, processor_tb.sv please do the following steps.
- Make sure that the paths for 9_ins_mem_tb.txt, 4_data_mem_tb.txt, 11_data_mem_out.txt are correctly set in DATA_RAM.sv, INS_RAM.sv, processor_tb.sv, multi_core_processor_tb.sv modules.
- Run 1_create_matrix.py and give the matrix dimensions and core-count in the multi-core processor. (For processor_tb.v simulation core-count should be 1)
- Run 3_dataCode_translate_for_tb.py to convert data (input matrices) into binary format.
- Run 5_multiply.py to multiply matrices using a python code to verify the answer from the simulation later.
- Run 8_machinecode_translation_for_tb.py to convert assembly code into machine code.
- Run the required verilog simulation in ModelSim/QuestaSim as mentioned above. (The binary values of the Data_memory will be stored in the 11_data_mem_out.txt file.
- Run 12_convert_back.py to create the answer matrix from the previous binary file.
- Run 14_compare_2_answers.py to verify that the simulation is correct or not.
- Demo of the multi-core processor can be found here. Demonstration of the design
- Documentation of the design - Final report (Please note that the codes in the report's appendix section are little bit old and instead of them use the codes in the github repository.)
- The Verilog implementation of the same design can be found here