dt-bindings: mtd: tegra-nand: Convert to json-schema

Convert the Tegra NAND controller bindings from the free-form text
format to json-schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>

Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml

@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra NAND Flash controller
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+  compatible:
+    const: nvidia,tegra20-nand
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: module clock
+
+  clock-names:
+    items:
+      - const: nand
+
+  resets:
+    items:
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: nand
+
+  operating-points-v2:
+    $ref: "/schemas/types.yaml#/definitions/phandle"
+
+  power-domains:
+    items:
+      - description: phandle to the core power domain
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: nand-controller.yaml
+
+patternProperties:
+  "^nand@[a-f0-9]$":
+    type: object
+    properties:
+      nand-ecc-mode:
+        description: String, operation mode of the NAND ecc mode.
+        const: hw
+
+      nand-ecc-algo:
+        enum: [ bch, rs ]
+
+      nand-ecc-strength:
+        enum: [ 4, 6, 8, 14, 16 ]
+
+      wp-gpios:
+        $ref: /schemas/types.yaml#/definitions/phandle-array
+        description: GPIO specifier for the write protect pin.
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra20-car.h>
+    #include <dt-bindings/gpio/tegra-gpio.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    nand-controller@70008000 {
+      compatible = "nvidia,tegra20-nand";
+      reg = <0x70008000 0x100>;
+      interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+      clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+      clock-names = "nand";
+      resets = <&tegra_car 13>;
+      reset-names = "nand";
+
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      nand@0 {
+        reg = <0>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        nand-bus-width = <8>;
+        nand-on-flash-bbt;
+        nand-ecc-algo = "bch";
+        nand-ecc-strength = <8>;
+        wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+      };
+    };