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RFE: OvmfPkg: Set MSR_IA32_FEATURE_CONTROL by following QEMU fw_cfg file #97
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Thanks, the description looks good. A few more questions:
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Design discussion started at http://thread.gmane.org/gmane.comp.bios.edk2.devel/14049 |
@hzzhan9: can you recommend a simple QEMU command line, and give guest kernel (or userspace) instructions for verifying the feature? Thanks! |
The S3 requirement needs clarification: |
Apparently S3 is required. I'm also attaching a minimal kernel module that can be used for reading any MSR on any CPU, for testing this feature. Just create any empty git repo with ... Sigh, github is stupid, it doesn't allow me to attach |
Under certain circumstances, QEMU exposes the "etc/msr_feature_control" fw_cfg file, with a 64-bit little endian value. The firmware is supposed to write this value to MSR_IA32_FEATURE_CONTROL (0x3a), on all processors, on the normal and the S3 resume boot paths. Utilize EFI_PEI_MPSERVICES_PPI to implement this feature. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Fixes: tianocore#97 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Posted series: |
Under certain circumstances, QEMU exposes the "etc/msr_feature_control" fw_cfg file, with a 64-bit little endian value. The firmware is supposed to write this value to MSR_IA32_FEATURE_CONTROL (0x3a), on all processors, on the normal and the S3 resume boot paths. Utilize EFI_PEI_MPSERVICES_PPI to implement this feature. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Fixes: tianocore#97 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Posted series |
Under certain circumstances, QEMU exposes the "etc/msr_feature_control" fw_cfg file, with a 64-bit little endian value. The firmware is supposed to write this value to MSR_IA32_FEATURE_CONTROL (0x3a), on all processors, on the normal and the S3 resume boot paths. Utilize EFI_PEI_MPSERVICES_PPI to implement this feature. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Fixes: tianocore#97 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
Posted series |
This (closed) item has been manually migrated to |
Hi,
A recent QEMU patch series [1] adds a new fw_cfg file "etc/msr_feature_control" to publish the value that the guest firmware is advised to write to MSR_IA32_FEATURE_CONTROL (MSR 0x3a). This should be supported by OVMF as well [2].
For some hardware features, e.g. Intel VMX and local MCE, OS usually expects certain bits in MSR_IA32_FEATURE_CONTROL are set by firmware. Using corresponding features (e.g access VMX MSRs) without setting those bits can result in #GP.
Instead of adding code to guest firmware everytime a new feature is added to QEMU, we can use a QEMU fw_cfg file to publish the advised value of MSR_IA32_FEATURE_CONTROL.
Path: etc/msr_feature_control
Format: one unsigned 64-bit integer which is the value that is advised to set to MSR_IA32_FEATURE_CONTROL.
Yes, firmware should set MSR_IA32_FEATURE_CONTROL at every boot. Firmware is expected to set MSR_IA32_FEATURE_CONTROL to the value in etc/msr_feature_control at S3 resume.
./configure --enable-kvm
).qemu-system-x86_64 -enable-kvm -smp 4 -cpu qemu64,+vmx -hda PATH_TO_GUEST_IMAGE -m 512
rdmsr -a 0x3a
It's expected to get 4 lines of '5', which means MSR_IA32_FEATURE_CONTROL on all CPUs are set to 5.
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