OvmfPkg: CloudHv: Reduce PIO and MMIO accesses #2942
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added 4 commits
June 3, 2022 18:26
The FW_BASE_ADDRESS value provided by OvmfPkgDefines.fdf.inc is incorrect for the CloudHv target. We know the generated firmware contains a PVH ELF header, meaning it will be loaded according to the address provided through this header. And since we know this address isn't going to change as it's part of CloudHvElfHeader.fdf.inc, we can hardcode it through a new include file CloudHvDefines.fdf.inc, which replaces the generic one OvmfPkgDefines.fdf.inc. With this change, we prevent the firmware from accessing MMIO addresses from the address range 0xffc00000-0xffffffff since we know the firmware hasn't been loaded on this address range. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
There are few places in the codebase assuming QemuFwCfg will be present and supported, which can cause some issues when trying to rely on the QemuFwCfgLibNull implementation of QemuFwCfgLib. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Since Cloud Hypervisor doesn't support the fw_cfg mechanism, it's more appropriate to rely on QemuFwCfgLibNull implementation of QemuFwCfgLib since it provides a null implementation that will not issue any PIO accesses to ports 0x510 and 0x511. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
Since Cloud Hypervisor doesn't emulate an A20 gate register on I/O port 0x92, it's better to avoid accessing it when the platform is identified as Cloud Hypervisor. Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com> Acked-by: Jiewen Yao <jiewen.yao@intel.com>
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From: Sebastien Boeuf sebastien.boeuf@intel.com
The goal of this series is to reduce the amount of inappropriate PIO
and MMIO accesses generated by the firmware when running on Cloud
Hypervisor.
For MMIO accesses, it is about providing the right base address where
the firmware will be loaded by the VMM in order to avoid unexpected
accesses to some address ranges.
For PIO accesses, it is about preventing some read/write to be performed
in the first place, as we know the underlying device is not emulated by
Cloud Hypervisor.
Signed-off-by: Sebastien Boeuf sebastien.boeuf@intel.com
Sebastien Boeuf (4):
OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
OvmfPkg: Check for QemuFwCfg availability before accessing it
OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
OvmfPkg/CloudHv/CloudHvDefines.fdf.inc | 65 +++++++++++++++++++
OvmfPkg/CloudHv/CloudHvX64.dsc | 4 +-
OvmfPkg/CloudHv/CloudHvX64.fdf | 2 +-
OvmfPkg/Library/PlatformInitLib/Platform.c | 13 ++--
.../QemuBootOrderLib/QemuBootOrderLib.c | 8 ++-
5 files changed, 82 insertions(+), 10 deletions(-)
create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc