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This project provides a basis for using the Red Pitaya (or now STEMlab 125-14) for data acquisition. This alone is nothing that can't be achieved with the standard libraries and images. But sometimes, having only two fast ADCs and two fast DACs is not enough. With the FPGA image and the server provided in this project, you can daisy chain multiple units and synchronize them to use the same clock. This allows for using all DACs and ADCs together without having to worry about phase shifts due to small clock speed differences. The general idea of this synchronization is to distribute the clock of a master device to the slave devices via the SATA daisy chain connectors. Depending on your networking hardware you can continuously acquire the signals of the fast ADCs at a decimation of up to 8 (15.625 MSamples/s). The data is written into an 8 MB ring buffer in the memory that can either send over the network (TCP/UDP) or directly written into a hard drive.
For building your own version you need
- the amount of Red Pitayas you need for your project
- SATA cables for the daisy chaining
- some cables for connecting the extension connector ports used for the synchronization signal
- soldering skills for changing the clock source of the ADCs
- a gigabit (or more) switch for connecting all the RPs to the network
- Some C and network programming knowledge.
The project does not only provide means for synchronization but also
- the ability to generate four tone sine signals on the fast DACs
- upload of LUTs for the slow DACs (currently only CPU based)
- access to the slow ADCs
- a watchdog mode for using e.g. an Arduino or Raspberry Pi as a security device for your whole setup
- an instant stop pin for stopping all DACs in case of a system failure
Since a certain amount of RAM has to be untouched by the operating system, a special image for the SD card is needed. For this, we would like to point out the excellent work of Pavel Demin and especially this page:
Reroute your slave's ADC clock source by resoldering the resistors according to this documentation. The required mode for this project is 'Directly from FPGA'.
Connect the master Red Pitaya with the first slave via a SATA cable. Then connect the first slave with the second slave and so on. In order to send a mutual trigger signal for starting the acquisition and the signal generation, you also have to connect the master's DIO5_P pin (see link) with the DIO0_P pin of all devices including the master.
In after installation of the Alpine image on an SD card, you should connect to the device via ssh and run
apk add git make gcc
To persist the changes on the SD card, add
/usr/local/ to the
lbu includes via
lbu include /usr/local/ and then run
lbu commit -d. The latter has to be run for every change you want to persist on the SD card. Within the
/root/ folder you should then clone the repository by typing
git clone https://github.com/tknopp/RedPitayaDAQServer.git
cd into RedPitayaDAQServer and run
make. Currently some scripts use an absolute path and therefore expect the repository to be cloned in that directory.
The daq_server_scpi is an exemplary server applications tailored for certain needs of the project creator. More documentation can be here ...
Building the bitfiles yourself
If you want to make changes to the FPGA design, you need to install Vivado. For this, we would like to point at the work of Pavel Demin again:
After following the installation steps, you need to clone the repository into a directory of your choice and then regenerate the IP cores and the project by running
Afterwards you can start Vivado and open the recreated project in
./build/fpga/firmware/RedPitayaDAQServer.xpr. Apply the changes you need and then create the bitfile by using 'Flow -> Generate Bitstream'. This runs the synthesis and implementation steps and output the Bitfile to
./build/fpga/firmware/RedPitayaDAQServer.runs/impl_1/system_wrapper.bit. Please note, that you have to create both the master and the slave image. This can be done by simply changing the value of xlconstant_masterslave. A '1' denotes the use of the internal ADC clock and is used for the master. A '0' selects the clock distributed via the daisy chain connectors and is therefore used for the slaves.
After creating the respective bitfile you need to copy it to your Red Pitayas. You can use
scp ./build/fpga/firmware/RedPitayaDAQServer.runs/impl_1/system_wrapper.bin root@<IP>:/root/RedPitayaDAQServer/bitfiles/<master,slave>.bin
for this. Set your IP and master/slave accordingly.
Since using git with Vivado can be annoying here are some hints how you can make your changes ready for git:
- If you only changed some stuff in the blockdesign, you just have to export the blockdesign to
./src/fpga/bdby using 'File -> Export -> Export Block Design' in Vivado.
- Changes to the project settings have to be done in
./src/fpga/build.tclin order to not lose the ability to recreate your changed project.
- For your own IP cores, just create a new directory in
./src/fpga/coresand copy and adapt the
core_config.tclof another core. Afterwards re-run
For this project, we asked several people from the Red Pitaya community for help. It all started with a blog post of Koheron on synchronizing multiple Red Pitayas. We extended their solution in order to also synchronize the ADCs and a discussion in their comment section was really helpful for that. We also used their implementation of PDM for the slow DACs (see link). Another big source of information was the work of Pavel Demin. The whole part of continuously reading the ADCs and sending the data via network was a great starting point for our own server.