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Use AES CFS als replacement for initial CFS now
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@tmeissner
tmeissner committed Jan 8, 2023
1 parent 3bd0835 commit 8ca5a02
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Showing 7 changed files with 49 additions and 122 deletions.
19 changes: 14 additions & 5 deletions rtl/core/neorv32_cfs_aes.vhd
View file
Expand Up @@ -65,6 +65,15 @@ end neorv32_cfs_aes;

architecture neorv32_cfs_rtl of neorv32_cfs_aes is

-- some convenient aliases
alias aes_base_c is cfs_base_c;
alias aes_size_c is cfs_size_c;
alias aes_ctrl_addr_c is cfs_reg0_addr_c;
alias aes_key_addr_c is cfs_reg1_addr_c;
alias aes_nonce_addr_c is cfs_reg2_addr_c;
alias aes_din_addr_c is cfs_reg3_addr_c;
alias aes_dout_addr_c is cfs_reg4_addr_c;

-- IO space: module base address --
-- WARNING: Do not modify the CFS base address or the CFS' occupied address
-- space as this might cause access collisions with other processor modules.
Expand Down Expand Up @@ -92,11 +101,11 @@ architecture neorv32_cfs_rtl of neorv32_cfs_aes is
signal read_acc_cnt : reg_acc_cnt_t(0 to 3);
signal write_acc_cnt : reg_acc_cnt_t(0 to 2);

constant AES_RESET : natural := 0; -- Reset key & din registers
constant CTR_START : natural := 1; -- 1st round of counter mode
constant AES_START : natural := 2; -- start AES engine (cleared with AES_END)
constant AES_RESET : natural := 0; -- Reset registers
constant CTR_START : natural := 1; -- 1st round of counter mode (cleared when AES processing begins)
constant AES_START : natural := 2; -- start AES engine (cleared when AES processing begins)
constant AES_END : natural := 3; -- AES engine finished
constant AES_IRQEN : natural := 4; -- AES engine finished
constant AES_IRQEN : natural := 4; -- Irq enable

begin

Expand Down Expand Up @@ -134,7 +143,7 @@ begin
write_acc_cnt <= (others => "00");
-- aes
aes_dout_accept <= '0';
--
-- cpu bus
ack_o <= '0';
data_o <= (others => '0');
elsif rising_edge(clk_i) then
Expand Down
21 changes: 5 additions & 16 deletions rtl/core/neorv32_package.vhd
View file
Expand Up @@ -160,7 +160,7 @@ package neorv32_package is

-- Custom Functions Subsystem (CFS) --
constant cfs_base_c : std_ulogic_vector(31 downto 0) := x"fffffe00"; -- base address
constant cfs_size_c : natural := 27*4; -- module's address space in bytes
constant cfs_size_c : natural := 32*4; -- module's address space in bytes
constant cfs_reg0_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe00";
constant cfs_reg1_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe04";
constant cfs_reg2_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe08";
Expand Down Expand Up @@ -188,15 +188,6 @@ package neorv32_package is
constant cfs_reg24_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe60";
constant cfs_reg25_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe64";
constant cfs_reg26_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe68";
--
constant aes_base_c : std_ulogic_vector(31 downto 0) := x"fffffe6c"; -- base address
constant aes_size_c : natural := 5*4; -- module's address space in bytes
constant aes_ctrl_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe6c";
constant aes_key_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe70";
constant aes_nonce_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe74";
constant aes_din_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe78";
constant aes_dout_addr_c : std_ulogic_vector(31 downto 0) := x"fffffe7c";


-- Pulse-Width Modulation Controller (PWM) --
constant pwm_base_c : std_ulogic_vector(31 downto 0) := x"fffffe80"; -- base address
Expand Down Expand Up @@ -1065,16 +1056,15 @@ package neorv32_package is
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_TRNG_FIFO : natural := 1; -- TRNG fifo depth, has to be a power of two, min 1
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS, AES in this case)?
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
IO_AES_EN : boolean := false -- implement AES(128) custom function?
IO_ONEWIRE_EN : boolean := false -- implement 1-wire interface (ONEWIRE)?
);
port (
-- Global control --
Expand Down Expand Up @@ -2217,14 +2207,13 @@ package neorv32_package is
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS, AES in this case)?
IO_SLINK_EN : boolean; -- implement stream link interface?
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean; -- implement 1-wire interface (ONEWIRE)?
IO_AES_EN : boolean -- implement AES(128) custom function?
IO_ONEWIRE_EN : boolean -- implement 1-wire interface (ONEWIRE)?
);
port (
-- host access --
Expand Down
9 changes: 4 additions & 5 deletions rtl/core/neorv32_sysinfo.vhd
View file
Expand Up @@ -76,14 +76,13 @@ entity neorv32_sysinfo is
IO_PWM_NUM_CH : natural; -- number of PWM channels to implement
IO_WDT_EN : boolean; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS, AES in this case)?
IO_SLINK_EN : boolean; -- implement stream link interface?
IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean; -- implement 1-wire interface (ONEWIRE)?
IO_AES_EN : boolean -- implement AES(128) custom function?
IO_ONEWIRE_EN : boolean -- implement 1-wire interface (ONEWIRE)?
);
port (
-- host access --
Expand Down Expand Up @@ -145,7 +144,7 @@ begin
sysinfo_mem(2)(13) <= bool_to_ulogic_f(is_simulation_c); -- is this a simulation?
sysinfo_mem(2)(14) <= bool_to_ulogic_f(ON_CHIP_DEBUGGER_EN); -- on-chip debugger implemented?
--
sysinfo_mem(2)(15) <= bool_to_ulogic_f(IO_AES_EN); -- '0'; -- reserved
sysinfo_mem(2)(15) <= '0'; -- reserved
-- IO --
sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN); -- general purpose input/output port unit (GPIO) implemented?
sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented?
Expand All @@ -154,7 +153,7 @@ begin
sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented?
sysinfo_mem(2)(21) <= bool_to_ulogic_f(boolean(IO_PWM_NUM_CH > 0)); -- pulse-width modulation unit (PWM) implemented?
sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented?
sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS, AES in this case) implemented?
sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented?
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_SLINK_EN); -- stream links (SLINK) implemented?
sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented?
Expand Down
68 changes: 12 additions & 56 deletions rtl/core/neorv32_top.vhd
View file
Expand Up @@ -131,16 +131,15 @@ entity neorv32_top is
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
IO_TRNG_FIFO : natural := 1; -- TRNG fifo depth, has to be a power of two, min 1
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS, AES in this case)
IO_CFS_CONFIG : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
IO_NEOLED_EN : boolean := false; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_NEOLED_TX_FIFO : natural := 1; -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)?
IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)?
IO_ONEWIRE_EN : boolean := false; -- implement 1-wire interface (ONEWIRE)?
IO_AES_EN : boolean := false -- implement AES(128) custom function?
IO_ONEWIRE_EN : boolean := false -- implement 1-wire interface (ONEWIRE)?
);
port (
-- Global control --
Expand Down Expand Up @@ -358,7 +357,7 @@ architecture neorv32_top_rtl of neorv32_top is
type resp_bus_id_t is (RESP_BUSKEEPER, RESP_IMEM, RESP_DMEM, RESP_BOOTROM, RESP_WISHBONE, RESP_GPIO,
RESP_MTIME, RESP_UART0, RESP_UART1, RESP_SPI, RESP_TWI, RESP_PWM, RESP_WDT,
RESP_TRNG, RESP_CFS, RESP_NEOLED, RESP_SYSINFO, RESP_OCD, RESP_SLINK, RESP_XIRQ,
RESP_GPTMR, RESP_XIP_CT, RESP_XIP_ACC, RESP_ONEWIRE, RESP_AES);
RESP_GPTMR, RESP_XIP_CT, RESP_XIP_ACC, RESP_ONEWIRE);

-- module response bus --
type resp_bus_t is array (resp_bus_id_t) of resp_bus_entry_t;
Expand All @@ -375,7 +374,6 @@ architecture neorv32_top_rtl of neorv32_top is
signal spi_irq : std_ulogic;
signal twi_irq : std_ulogic;
signal cfs_irq : std_ulogic;
signal aes_irq : std_ulogic;
signal neoled_irq : std_ulogic;
signal slink_tx_irq : std_ulogic;
signal slink_rx_irq : std_ulogic;
Expand Down Expand Up @@ -412,7 +410,6 @@ begin
cond_sel_string_f(IO_WDT_EN, "WDT ", "") &
cond_sel_string_f(IO_TRNG_EN, "TRNG ", "") &
cond_sel_string_f(IO_CFS_EN, "CFS ", "") &
cond_sel_string_f(IO_AES_EN, "AES ", "") &
cond_sel_string_f(io_slink_en_c, "SLINK ", "") &
cond_sel_string_f(IO_NEOLED_EN, "NEOLED ", "") &
cond_sel_string_f(boolean(XIRQ_NUM_CH > 0), "XIRQ ", "") &
Expand Down Expand Up @@ -630,7 +627,7 @@ begin

-- fast interrupt requests (FIRQs) - triggers are SINGLE-SHOT --
fast_irq(00) <= wdt_irq; -- HIGHEST PRIORITY - watchdog
fast_irq(01) <= cfs_irq; -- custom functions subsystem
fast_irq(01) <= cfs_irq; -- custom functions subsystem (AES in this case)
fast_irq(02) <= uart0_rxd_irq; -- primary UART (UART0) RX
fast_irq(03) <= uart0_txd_irq; -- primary UART (UART0) TX
fast_irq(04) <= uart1_rxd_irq; -- secondary UART (UART1) RX
Expand All @@ -644,7 +641,7 @@ begin
fast_irq(12) <= gptmr_irq; -- general purpose timer
fast_irq(13) <= onewire_irq; -- ONEWIRE operation done
--
fast_irq(14) <= aes_irq; -- reserved
fast_irq(14) <= '0'; -- reserved
fast_irq(15) <= '0'; -- LOWEST PRIORITY - reserved


Expand Down Expand Up @@ -1021,14 +1018,13 @@ begin


-- Custom Functions Subsystem (CFS) -------------------------------------------------------
-- AES in this case
-- -------------------------------------------------------------------------------------------
neorv32_cfs_inst_true:
if (IO_CFS_EN = true) generate
neorv32_cfs_inst: neorv32_cfs
neorv32_cfs_aes_inst: neorv32_cfs_aes
generic map (
CFS_CONFIG => IO_CFS_CONFIG, -- custom CFS configuration generic
CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
CFS_OUT_SIZE => IO_CFS_OUT_SIZE -- size of CFS output conduit in bits
AES_CONFIG => 32x"0" -- custom AES configuration generic
)
port map (
-- host access --
Expand All @@ -1042,19 +1038,10 @@ begin
data_o => resp_bus(RESP_CFS).rdata, -- data out
ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge
err_o => resp_bus(RESP_CFS).err, -- access error
-- clock generator --
clkgen_en_o => cfs_cg_en, -- enable clock generator
clkgen_i => clk_gen, -- "clock" inputs
-- interrupt --
irq_o => cfs_irq, -- interrupt request
-- custom io (conduit) --
cfs_in_i => cfs_in_i, -- custom inputs
cfs_out_o => cfs_out_o -- custom outputs
irq_o => cfs_irq -- interrupt request
);
end generate;

neorv32_cfs_inst_false:
if (IO_CFS_EN = false) generate
else generate
resp_bus(RESP_CFS) <= resp_bus_entry_terminate_c;
--
cfs_cg_en <= '0';
Expand All @@ -1063,36 +1050,6 @@ begin
end generate;


-- AES128 Custom Function (AES) -------------------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_cfs_aes_inst_true:
if (IO_AES_EN = true) generate
neorv32_cfs_aes_inst: neorv32_cfs_aes
generic map (
AES_CONFIG => 32x"0" -- custom AES configuration generic
)
port map (
-- host access --
clk_i => clk_i, -- global clock line
rstn_i => rstn_int, -- global reset line, low-active, use as async
priv_i => p_bus.priv, -- current CPU privilege mode
addr_i => p_bus.addr, -- address
rden_i => io_rden, -- read enable
wren_i => io_wren, -- word write enable
data_i => p_bus.wdata, -- data in
data_o => resp_bus(RESP_AES).rdata, -- data out
ack_o => resp_bus(RESP_AES).ack, -- transfer acknowledge
err_o => resp_bus(RESP_AES).err, -- access error
-- interrupt --
irq_o => aes_irq -- interrupt request
);
else generate
resp_bus(RESP_AES) <= resp_bus_entry_terminate_c;
--
aes_irq <= '0';
end generate;


-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
-- -------------------------------------------------------------------------------------------
neorv32_gpio_inst_true:
Expand Down Expand Up @@ -1699,14 +1656,13 @@ begin
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS, AES in this case)?
IO_SLINK_EN => io_slink_en_c, -- implement stream link interface?
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
IO_XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external interrupt (XIRQ) channels to implement
IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)?
IO_XIP_EN => IO_XIP_EN, -- implement execute in place module (XIP)?
IO_ONEWIRE_EN => IO_ONEWIRE_EN, -- implement 1-wire interface (ONEWIRE)?
IO_AES_EN => IO_AES_EN -- implement AES(128) custom function?
IO_ONEWIRE_EN => IO_ONEWIRE_EN -- implement 1-wire interface (ONEWIRE)?
)
port map (
-- host access --
Expand Down
6 changes: 3 additions & 3 deletions sw/example/demo_aes/main.c
View file
Expand Up @@ -65,10 +65,10 @@ int main() {

neorv32_rte_setup();
// install AES interrupt handler
neorv32_rte_handler_install(AES_RTE_ID, aes_firq_handler);
neorv32_rte_handler_install(CFS_RTE_ID, aes_firq_handler);

// enable interrupt
neorv32_cpu_irq_enable(AES_FIRQ_ENABLE); // enable GPTMR FIRQ channel
neorv32_cpu_irq_enable(CFS_FIRQ_ENABLE); // enable GPTMR FIRQ channel
neorv32_cpu_eint(); // enable global interrupt flag

neorv32_aes_setup(key, nonce, 1);
Expand All @@ -92,7 +92,7 @@ int main() {
// Interrupt service routine
void aes_firq_handler(void) {

neorv32_cpu_csr_write(CSR_MIP, ~(1<<AES_FIRQ_PENDING));
neorv32_cpu_csr_write(CSR_MIP, ~(1<<CFS_FIRQ_PENDING));
aes_irq = 1;

}
28 changes: 1 addition & 27 deletions sw/lib/include/neorv32.h
View file
Expand Up @@ -594,13 +594,6 @@ enum NEORV32_CLOCK_PRSC_enum {
#define CFS_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define CFS_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name AES Custom Functions (CFS) */
/**@{*/
#define AES_FIRQ_ENABLE CSR_MIE_FIRQ1E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
#define AES_FIRQ_PENDING CSR_MIP_FIRQ1P /**< MIP CSR bit (#NEORV32_CSR_MIP_enum) */
#define AES_RTE_ID RTE_TRAP_FIRQ_1 /**< RTE entry code (#NEORV32_RTE_TRAP_enum) */
#define AES_TRAP_CODE TRAP_CODE_FIRQ_1 /**< MCAUSE CSR trap code (#NEORV32_EXCEPTION_CODES_enum) */
/**@}*/
/** @name Primary Universal Asynchronous Receiver/Transmitter (UART0) */
/**@{*/
#define UART0_RX_FIRQ_ENABLE CSR_MIE_FIRQ2E /**< MIE CSR bit (#NEORV32_CSR_MIE_enum) */
Expand Down Expand Up @@ -753,7 +746,7 @@ typedef struct __attribute__((packed,aligned(4))) {
/**@{*/
/** CFS module prototype */
typedef struct __attribute__((packed,aligned(4))) {
uint32_t REG[27]; /**< offset 4*0..4*31: CFS register 0..31, user-defined */
uint32_t REG[32]; /**< offset 4*0..4*31: CFS register 0..31, user-defined */
} neorv32_cfs_t;

/** CFS base address */
Expand All @@ -763,25 +756,6 @@ typedef struct __attribute__((packed,aligned(4))) {
#define NEORV32_CFS (*((volatile neorv32_cfs_t*) (NEORV32_CFS_BASE)))
/**@}*/

/**********************************************************************//**
* @name IO Device: AES Custom Functions (AES)
**************************************************************************/
/**@{*/
/** AES module prototype */
typedef struct __attribute__((packed,aligned(4))) {
uint32_t CTRL;
uint32_t KEY;
uint32_t NONCE;
uint32_t WDATA;
uint32_t RDATA;
} neorv32_aes_t;

/** AES base address */
#define NEORV32_AES_BASE (0xFFFFFE6CU)

/** AES module hardware access (#neorv32_aes_t) */
#define NEORV32_AES (*((volatile neorv32_aes_t*) (NEORV32_AES_BASE)))
/**@}*/

/**********************************************************************//**
* @name IO Device: Pulse Width Modulation Controller (PWM)
Expand Down

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