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refactor stmf32f4xx chip code into multiple crates #1803

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May 4, 2020
Merged

refactor stmf32f4xx chip code into multiple crates #1803

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b0419a4
refactor stmf32f4xx chips to remove need for cfg
hudson-ayers Apr 27, 2020
5545e9b
address gendx review
hudson-ayers Apr 28, 2020
818832f
remove features from cargo.toml
hudson-ayers May 4, 2020
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2 changes: 2 additions & 0 deletions Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,8 @@ members = [
"chips/sam4l",
"chips/sifive",
"chips/stm32f3xx",
"chips/stm32f429zi",
hudson-ayers marked this conversation as resolved.
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"chips/stm32f446re",
"chips/stm32f4xx",
"kernel",
"libraries/enum_primitive",
Expand Down
14 changes: 7 additions & 7 deletions boards/components/src/hd44780.rs
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Expand Up @@ -5,19 +5,19 @@
//! ```rust
//! let lcd = components::hd44780::HD44780Component::new(board_kernel, mux_alarm).finalize(
//! components::hd44780_component_helper!(
//! stm32f4xx::tim2::Tim2,
//! stm32f429zi::tim2::Tim2,
//! // rs pin
//! stm32f4xx::gpio::PinId::PF13.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PF13.get_pin().as_ref().unwrap(),
//! // en pin
//! stm32f4xx::gpio::PinId::PE11.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PE11.get_pin().as_ref().unwrap(),
//! // data 4 pin
//! stm32f4xx::gpio::PinId::PF14.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PF14.get_pin().as_ref().unwrap(),
//! // data 5 pin
//! stm32f4xx::gpio::PinId::PE13.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PE13.get_pin().as_ref().unwrap(),
//! // data 6 pin
//! stm32f4xx::gpio::PinId::PF15.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PF15.get_pin().as_ref().unwrap(),
//! // data 7 pin
//! stm32f4xx::gpio::PinId::PG14.get_pin().as_ref().unwrap()
//! stm32f429zi::gpio::PinId::PG14.get_pin().as_ref().unwrap()
//! )
//! );
//! ```
Expand Down
4 changes: 2 additions & 2 deletions boards/components/src/l3gd20.rs
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Expand Up @@ -8,9 +8,9 @@
//! let lcd = components::l3gd20::L3gd20SpiComponent::new(board_kernel).finalize(
//! components::l3gd20_spi_component_helper!(
//! // spi type
//! stm32f4xx::spi::Spi,
//! stm32f429zi::spi::Spi,
//! // chip select
//! stm32f4xx::gpio::PinId::PE03,
//! stm32f429zi::gpio::PinId::PE03,
//! // spi mux
//! spi_mux
//! )
Expand Down
2 changes: 1 addition & 1 deletion boards/nucleo_f429zi/Cargo.toml
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Expand Up @@ -10,4 +10,4 @@ components = { path = "../components" }
cortexm4 = { path = "../../arch/cortex-m4" }
capsules = { path = "../../capsules" }
kernel = { path = "../../kernel" }
stm32f4xx = { path = "../../chips/stm32f4xx", features = ["stm32f429zi"] }
stm32f429zi = { path = "../../chips/stm32f429zi" }
6 changes: 3 additions & 3 deletions boards/nucleo_f429zi/src/io.rs
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Expand Up @@ -9,8 +9,8 @@ use kernel::hil::led;
use kernel::hil::uart;
use kernel::hil::uart::Configure;

use stm32f4xx;
use stm32f4xx::gpio::PinId;
use stm32f429zi;
use stm32f429zi::gpio::PinId;

use crate::CHIP;
use crate::PROCESSES;
Expand Down Expand Up @@ -40,7 +40,7 @@ impl Write for Writer {

impl IoWrite for Writer {
fn write(&mut self, buf: &[u8]) {
let uart = unsafe { &mut stm32f4xx::usart::USART3 };
let uart = unsafe { &mut stm32f429zi::usart::USART3 };

if !self.initialized {
self.initialized = true;
Expand Down
216 changes: 108 additions & 108 deletions boards/nucleo_f429zi/src/main.rs
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2 changes: 1 addition & 1 deletion boards/nucleo_f446re/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -10,4 +10,4 @@ components = { path = "../components" }
cortexm4 = { path = "../../arch/cortex-m4" }
capsules = { path = "../../capsules" }
kernel = { path = "../../kernel" }
stm32f4xx = { path = "../../chips/stm32f4xx", features = ["stm32f446re"] }
stm32f446re = { path = "../../chips/stm32f446re" }
6 changes: 3 additions & 3 deletions boards/nucleo_f446re/src/io.rs
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Expand Up @@ -9,8 +9,8 @@ use kernel::hil::led;
use kernel::hil::uart;
use kernel::hil::uart::Configure;

use stm32f4xx;
use stm32f4xx::gpio::PinId;
use stm32f446re;
use stm32f446re::gpio::PinId;

use crate::CHIP;
use crate::PROCESSES;
Expand Down Expand Up @@ -40,7 +40,7 @@ impl Write for Writer {

impl IoWrite for Writer {
fn write(&mut self, buf: &[u8]) {
let uart = unsafe { &mut stm32f4xx::usart::USART2 };
let uart = unsafe { &mut stm32f446re::usart::USART2 };

if !self.initialized {
self.initialized = true;
Expand Down
44 changes: 22 additions & 22 deletions boards/nucleo_f446re/src/main.rs
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Expand Up @@ -30,7 +30,7 @@ static mut PROCESSES: [Option<&'static dyn kernel::procs::ProcessType>; NUM_PROC
[None, None, None, None];

// Static reference to chip for panic dumps.
static mut CHIP: Option<&'static stm32f4xx::chip::Stm32f4xx> = None;
static mut CHIP: Option<&'static stm32f446re::chip::Stm32f4xx> = None;

// How should the kernel respond when a process faults.
const FAULT_RESPONSE: kernel::procs::FaultResponse = kernel::procs::FaultResponse::Panic;
Expand Down Expand Up @@ -59,7 +59,7 @@ struct NucleoF446RE {
button: &'static capsules::button::Button<'static>,
alarm: &'static capsules::alarm::AlarmDriver<
'static,
VirtualMuxAlarm<'static, stm32f4xx::tim2::Tim2<'static>>,
VirtualMuxAlarm<'static, stm32f446re::tim2::Tim2<'static>>,
>,
}

Expand All @@ -82,9 +82,9 @@ impl Platform for NucleoF446RE {

/// Helper function called during bring-up that configures DMA.
unsafe fn setup_dma() {
use stm32f4xx::dma1::{Dma1Peripheral, DMA1};
use stm32f4xx::usart;
use stm32f4xx::usart::USART2;
use stm32f446re::dma1::{Dma1Peripheral, DMA1};
use stm32f446re::usart;
use stm32f446re::usart::USART2;

DMA1.enable_clock();

Expand All @@ -108,9 +108,9 @@ unsafe fn setup_dma() {

/// Helper function called during bring-up that configures multiplexed I/O.
unsafe fn set_pin_primary_functions() {
use stm32f4xx::exti::{LineId, EXTI};
use stm32f4xx::gpio::{AlternateFunction, Mode, PinId, PortId, PORT};
use stm32f4xx::syscfg::SYSCFG;
use stm32f446re::exti::{LineId, EXTI};
use stm32f446re::gpio::{AlternateFunction, Mode, PinId, PortId, PORT};
use stm32f446re::syscfg::SYSCFG;

SYSCFG.enable_clock();

Expand Down Expand Up @@ -148,20 +148,20 @@ unsafe fn set_pin_primary_functions() {
EXTI.associate_line_gpiopin(LineId::Exti13, pin);
});
// EXTI13 interrupts is delivered at IRQn 40 (EXTI15_10)
cortexm4::nvic::Nvic::new(stm32f4xx::nvic::EXTI15_10).enable();
cortexm4::nvic::Nvic::new(stm32f446re::nvic::EXTI15_10).enable();
}

/// Helper function for miscellaneous peripheral functions
unsafe fn setup_peripherals() {
use stm32f4xx::tim2::TIM2;
use stm32f446re::tim2::TIM2;

// USART2 IRQn is 38
cortexm4::nvic::Nvic::new(stm32f4xx::nvic::USART2).enable();
cortexm4::nvic::Nvic::new(stm32f446re::nvic::USART2).enable();

// TIM2 IRQn is 28
TIM2.enable_clock();
TIM2.start();
cortexm4::nvic::Nvic::new(stm32f4xx::nvic::TIM2).enable();
cortexm4::nvic::Nvic::new(stm32f446re::nvic::TIM2).enable();
}

/// Reset Handler.
Expand All @@ -172,7 +172,7 @@ unsafe fn setup_peripherals() {
/// execution begins here.
#[no_mangle]
pub unsafe fn reset_handler() {
stm32f4xx::init();
stm32f446re::stm32f4xx::init();

// We use the default HSI 16Mhz clock

Expand All @@ -192,17 +192,17 @@ pub unsafe fn reset_handler() {
DynamicDeferredCall::set_global_instance(dynamic_deferred_caller);

let chip = static_init!(
stm32f4xx::chip::Stm32f4xx,
stm32f4xx::chip::Stm32f4xx::new()
stm32f446re::chip::Stm32f4xx,
stm32f446re::chip::Stm32f4xx::new()
);
CHIP = Some(chip);

// UART

// Create a shared UART channel for kernel debug.
stm32f4xx::usart::USART2.enable_clock();
stm32f446re::usart::USART2.enable_clock();
let uart_mux = components::console::UartMuxComponent::new(
&stm32f4xx::usart::USART2,
&stm32f446re::usart::USART2,
115200,
dynamic_deferred_caller,
)
Expand Down Expand Up @@ -248,27 +248,27 @@ pub unsafe fn reset_handler() {

// Clock to Port A is enabled in `set_pin_primary_functions()`
let led = components::led::LedsComponent::new().finalize(components::led_component_helper!((
stm32f4xx::gpio::PinId::PA05.get_pin().as_ref().unwrap(),
stm32f446re::gpio::PinId::PA05.get_pin().as_ref().unwrap(),
kernel::hil::gpio::ActivationMode::ActiveHigh
)));

// BUTTONs
let button = components::button::ButtonComponent::new(board_kernel).finalize(
components::button_component_helper!((
stm32f4xx::gpio::PinId::PC13.get_pin().as_ref().unwrap(),
stm32f446re::gpio::PinId::PC13.get_pin().as_ref().unwrap(),
kernel::hil::gpio::ActivationMode::ActiveLow,
kernel::hil::gpio::FloatingState::PullNone
)),
);

// ALARM
let tim2 = &stm32f4xx::tim2::TIM2;
let tim2 = &stm32f446re::tim2::TIM2;
let mux_alarm = components::alarm::AlarmMuxComponent::new(tim2).finalize(
components::alarm_mux_component_helper!(stm32f4xx::tim2::Tim2),
components::alarm_mux_component_helper!(stm32f446re::tim2::Tim2),
);

let alarm = components::alarm::AlarmDriverComponent::new(board_kernel, mux_alarm)
.finalize(components::alarm_component_helper!(stm32f4xx::tim2::Tim2));
.finalize(components::alarm_component_helper!(stm32f446re::tim2::Tim2));

let nucleo_f446re = NucleoF446RE {
console: console,
Expand Down
14 changes: 7 additions & 7 deletions capsules/src/hd44780.rs
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Expand Up @@ -27,19 +27,19 @@
//! ```rust
//! let lcd = components::hd44780::HD44780Component::new(board_kernel, mux_alarm).finalize(
//! components::hd44780_component_helper!(
//! stm32f4xx::tim2::Tim2,
//! stm32f429zi::tim2::Tim2,
//! // rs pin
//! stm32f4xx::gpio::PinId::PF13.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PF13.get_pin().as_ref().unwrap(),
//! // en pin
//! stm32f4xx::gpio::PinId::PE11.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PE11.get_pin().as_ref().unwrap(),
//! // data 4 pin
//! stm32f4xx::gpio::PinId::PF14.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PF14.get_pin().as_ref().unwrap(),
//! // data 5 pin
//! stm32f4xx::gpio::PinId::PE13.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PE13.get_pin().as_ref().unwrap(),
//! // data 6 pin
//! stm32f4xx::gpio::PinId::PF15.get_pin().as_ref().unwrap(),
//! stm32f429zi::gpio::PinId::PF15.get_pin().as_ref().unwrap(),
//! // data 7 pin
//! stm32f4xx::gpio::PinId::PG14.get_pin().as_ref().unwrap()
//! stm32f429zi::gpio::PinId::PG14.get_pin().as_ref().unwrap()
//! )
//! );
//! ```
Expand Down
12 changes: 12 additions & 0 deletions chips/stm32f429zi/Cargo.toml
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@@ -0,0 +1,12 @@
[package]
name = "stm32f429zi"
version = "0.1.0"
authors = ["Tock Project Developers <tock-dev@googlegroups.com>"]
edition = "2018"

[dependencies]
cortexm4 = { path = "../../arch/cortex-m4" }
kernel = { path = "../../kernel" }
stm32f4xx = { path = "../stm32f4xx" }
tock_rt0 = { path = "../../libraries/tock-rt0" }
enum_primitive = { path = "../../libraries/enum_primitive" }
5 changes: 5 additions & 0 deletions chips/stm32f429zi/README.md
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@@ -0,0 +1,5 @@
# ST Micro stm32f429zi MCU

Builds upon the `stm32f4xx` crate and includes hardware setup that is specific to this version of
the stm32f4xx series. Boards that include an stm32f429zi MCU should use this crate as a dependency
and not the `stm32f4xx` crate.
99 changes: 99 additions & 0 deletions chips/stm32f429zi/src/irqs.rs
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@@ -0,0 +1,99 @@
use cortexm4::generic_isr;

// STM32F42xxx and STM32F43xxx has total of 91 interrupts
#[cfg_attr(all(target_arch = "arm", target_os = "none"), link_section = ".irqs")]
// used Ensures that the symbol is kept until the final binary
#[cfg_attr(all(target_arch = "arm", target_os = "none"), used)]
pub static IRQS: [unsafe extern "C" fn(); 91] = [
generic_isr, // WWDG (0)
generic_isr, // PVD (1)
generic_isr, // TAMP_STAMP (2)
generic_isr, // RTC_WKUP (3)
generic_isr, // FLASH (4)
generic_isr, // RCC (5)
generic_isr, // EXTI0 (6)
generic_isr, // EXTI1 (7)
generic_isr, // EXTI2 (8)
generic_isr, // EXTI3 (9)
generic_isr, // EXTI4 (10)
generic_isr, // DMA1_Stream0 (11)
generic_isr, // DMA1_Stream1 (12)
generic_isr, // DMA1_Stream2 (13)
generic_isr, // DMA1_Stream3 (14)
generic_isr, // DMA1_Stream4 (15)
generic_isr, // DMA1_Stream5 (16)
generic_isr, // DMA1_Stream6 (17)
generic_isr, // ADC (18)
generic_isr, // CAN1_TX (19)
generic_isr, // CAN1_RX0 (20)
generic_isr, // CAN1_RX1 (21)
generic_isr, // CAN1_SCE (22)
generic_isr, // EXTI9_5 (23)
generic_isr, // TIM1_BRK_TIM9 (24)
generic_isr, // TIM1_UP_TIM10 (25)
generic_isr, // TIM1_TRG_COM_TIM11 (26)
generic_isr, // TIM1_CC (27)
generic_isr, // TIM2 (28)
generic_isr, // TIM3 (29)
generic_isr, // TIM4 (30)
generic_isr, // I2C1_EV (31)
generic_isr, // I2C1_ER (32)
generic_isr, // I2C2_EV (33)
generic_isr, // I2C2_ER (34)
generic_isr, // SPI1 (35)
generic_isr, // SPI2 (36)
generic_isr, // USART1 (37)
generic_isr, // USART2 (38)
generic_isr, // USART3 (39)
generic_isr, // EXTI15_10 (40)
generic_isr, // RTC_Alarm (41)
generic_isr, // OTG_FS_WKUP (42)
generic_isr, // TIM8_BRK_TIM12 (43)
generic_isr, // TIM8_UP_TIM13 (44)
generic_isr, // TIM8_TRG_COM_TIM14 (45)
generic_isr, // TIM8_CC (46)
generic_isr, // DMA1_Stream7 (47)
generic_isr, // FMC (48)
generic_isr, // SDIO (49)
generic_isr, // TIM5 (50)
generic_isr, // SPI3 (51)
generic_isr, // UART4 (52)
generic_isr, // UART5 (53)
generic_isr, // TIM6_DAC (54)
generic_isr, // TIM7 (55)
generic_isr, // DMA2_Stream0 (56)
generic_isr, // DMA2_Stream1 (57)
generic_isr, // DMA2_Stream2 (58)
generic_isr, // DMA2_Stream3 (59)
generic_isr, // DMA2_Stream4 (60)
generic_isr, // ETH (61)
generic_isr, // ETH_WKUP (62)
generic_isr, // CAN2_TX (63)
generic_isr, // CAN2_RX0 (64)
generic_isr, // CAN2_RX1 (65)
generic_isr, // CAN2_SCE (66)
generic_isr, // OTG_FS (67)
generic_isr, // DMA2_Stream5 (68)
generic_isr, // DMA2_Stream6 (69)
generic_isr, // DMA2_Stream7 (70)
generic_isr, // USART6 (71)
generic_isr, // I2C3_EV (72)
generic_isr, // I2C3_ER (73)
generic_isr, // OTG_HS_EP1_OUT (74)
generic_isr, // OTG_HS_EP1_IN (75)
generic_isr, // OTG_HS_WKUP (76)
generic_isr, // OTG_HS (77)
generic_isr, // DCMI (78)
generic_isr, // CRYP (79)
generic_isr, // HASH_RNG (80)
generic_isr, // FPU (81)
generic_isr, // USART7 (82)
generic_isr, // USART8 (83)
generic_isr, // SPI4 (84)
generic_isr, // SPI5 (85)
generic_isr, // SPI6 (86)
generic_isr, // SAI1 (87)
generic_isr, // LCD-TFT (88)
generic_isr, // LCD-TFT (89)
generic_isr, // DMA2D(90)
];
7 changes: 7 additions & 0 deletions chips/stm32f429zi/src/lib.rs
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@@ -0,0 +1,7 @@
#![no_std]

pub use stm32f4xx;
pub use stm32f4xx::{chip, dbg, dma1, exti, gpio, nvic, rcc, spi, syscfg, tim2, usart};

pub mod irqs;
pub mod stm32f429zi_nvic;