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riscv mtimer: don't directly modify interrupt enables #2134

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Oct 2, 2020
Merged

riscv mtimer: don't directly modify interrupt enables #2134

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11 changes: 5 additions & 6 deletions arch/rv32i/src/machine_timer.rs
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Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
//! Create a timer using the Machine Timer registers.

use crate::csr;
use kernel::common::cells::OptionalCell;
use kernel::common::registers::{register_structs, ReadWrite};
use kernel::common::StaticRef;
Expand Down Expand Up @@ -68,7 +67,6 @@ impl<'a> time::Alarm<'a> for MachineTimer<'a> {
}

fn set_alarm(&self, reference: Self::Ticks, dt: Self::Ticks) {
csr::CSR.mie.modify(csr::mie::mie::mtimer::CLEAR);
// This does not handle the 64-bit wraparound case.
// Because mtimer fires if the counter is >= the compare,
// handling wraparound requires setting compare to the
Expand All @@ -93,8 +91,6 @@ impl<'a> time::Alarm<'a> for MachineTimer<'a> {
regs.compare_low.set(0xFFFF_FFFF);
regs.compare_high.set(high);
regs.compare_low.set(low);

csr::CSR.mie.modify(csr::mie::mie::mtimer::SET);
}

fn get_alarm(&self) -> Self::Ticks {
Expand Down Expand Up @@ -157,10 +153,13 @@ impl kernel::SchedulerTimer for MachineTimer<'_> {
}

fn arm(&self) {
csr::CSR.mie.modify(csr::mie::mie::mtimer::SET);
// Arm and disarm are optional, but controlling the mtimer interrupt
// should be re-enabled if Tock moves to a design that allows direct control of
// interrupt enables
//csr::CSR.mie.modify(csr::mie::mie::mtimer::SET);
}

fn disarm(&self) {
csr::CSR.mie.modify(csr::mie::mie::mtimer::CLEAR);
//csr::CSR.mie.modify(csr::mie::mie::mtimer::CLEAR);
}
}