Supporting wire assignments.

tomahawkins · May 18, 2014 · c2f80ca · c2f80ca
1 parent 9450bc1
commit c2f80ca
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Showing 2 changed files with 32 additions and 19 deletions.
diff --git a/Language/Verilog/AST.hs b/Language/Verilog/AST.hs
@@ -31,10 +31,10 @@ instance Show Module where
 
 data ModuleItem
   = Parameter (Maybe Range) Identifier Expr
-  | Input     (Maybe Range) [(Identifier, Maybe Range)]
-  | Output    (Maybe Range) [(Identifier, Maybe Range)]
-  | Inout     (Maybe Range) [(Identifier, Maybe Range)]
-  | Wire      (Maybe Range) [(Identifier, Maybe Range)]
+  | Input     (Maybe Range) [Identifier]
+  | Output    (Maybe Range) [Identifier]
+  | Inout     (Maybe Range) [Identifier]
+  | Wire      (Maybe Range) [(Identifier, Maybe Expr)]
   | Reg       (Maybe Range) [(Identifier, Maybe Range)]
   | Initial    Stmt
   | Always     Sense Stmt
@@ -47,11 +47,11 @@ type PortBinding = (Identifier, Maybe Expr)
 instance Show ModuleItem where
   show a = case a of
     Parameter r n e -> printf "parameter %s%s = %s;" (showRange r) n (show e)
-    Input     r a   -> printf "input  %s%s;" (showRange r) (commas [ a ++ showRange r | (a, r) <- a ])
-    Output    r a   -> printf "output %s%s;" (showRange r) (commas [ a ++ showRange r | (a, r) <- a ])
-    Inout     r a   -> printf "inout  %s%s;" (showRange r) (commas [ a ++ showRange r | (a, r) <- a ])
-    Wire      r a   -> printf "wire   %s%s;" (showRange r) (commas [ a ++ showRange r | (a, r) <- a ])
-    Reg       r a   -> printf "reg    %s%s;" (showRange r) (commas [ a ++ showRange r | (a, r) <- a ])
+    Input     r a   -> printf "input  %s%s;" (showRange r) (commas a)
+    Output    r a   -> printf "output %s%s;" (showRange r) (commas a)
+    Inout     r a   -> printf "inout  %s%s;" (showRange r) (commas a)
+    Wire      r a   -> printf "wire   %s%s;" (showRange r) (commas [ a ++ showAssign r | (a, r) <- a ])
+    Reg       r a   -> printf "reg    %s%s;" (showRange r) (commas [ a ++ showRange  r | (a, r) <- a ])
     Initial   a     -> printf "initial\n%s" $ indent $ show a
     Always    a b   -> printf "always @(%s)\n%s" (show a) $ indent $ show b
     Assign    a b   -> printf "assign %s = %s;" (show a) (show b)
@@ -61,6 +61,10 @@ instance Show ModuleItem where
     where
     showPorts :: Show a => [(Identifier, Maybe a)] -> String
     showPorts ports = printf "(%s)" $ commas [ printf ".%s(%s)" i (if isJust arg then show $ fromJust arg else "") | (i, arg) <- ports ]
+    showAssign :: Maybe Expr -> String
+    showAssign a = case a of
+      Nothing -> ""
+      Just a -> printf " = %s" $ show a
 
 showRange :: Maybe Range -> String
 showRange Nothing = ""

diff --git a/Language/Verilog/Parser/Parse.y b/Language/Verilog/Parser/Parse.y
@@ -175,22 +175,31 @@ ModuleItems :: { [ModuleItem] }
 
 ModuleItem :: { ModuleItem }
 : "parameter" MaybeRange Identifier "=" Expr ";"        { Parameter $2 $3 $5 }
-| Net MaybeRange Declarations ";"                       { $1 $2 $3 }
+| "input"  MaybeRange Identifiers ";"                   { Input  $2 $3 }
+| "output" MaybeRange Identifiers ";"                   { Output $2 $3 }
+| "inout"  MaybeRange Identifiers ";"                   { Inout  $2 $3 }
+| "reg"    MaybeRange RegDeclarations ";"               { Reg    $2 $3 }
+| "wire"   MaybeRange WireDeclarations ";"              { Wire   $2 $3 }
 | "assign" LHS "=" Expr ";"                             { Assign $2 $4 }
 | "initial" Stmt                                        { Initial $2 }
 | "always" "@" "(" Sense ")" Stmt                       { Always $4 $6 }
 | Identifier ParameterBindings Identifier Bindings ";"  { Instance $1 $2 $3 $4 }
 
-Net :: { Maybe Range -> [(Identifier, Maybe Range)] -> ModuleItem }
-: "input"   { Input   }
-| "output"  { Output  }
-| "inout"   { Inout   }
-| "wire"    { Wire    }
-| "reg"     { Reg     }
+Identifiers :: { [Identifier] }
+:                 Identifier { [$1] }
+| Identifiers "," Identifier { $1 ++ [$3] }
 
-Declarations :: { [(Identifier, Maybe Range)] }
-:                  Identifier MaybeRange    { [($1, $2)]       }
-| Declarations "," Identifier MaybeRange    { $1 ++ [($3, $4)] }
+RegDeclarations :: { [(Identifier, Maybe Range)] }
+:                     Identifier MaybeRange    { [($1, $2)]       }
+| RegDeclarations "," Identifier MaybeRange    { $1 ++ [($3, $4)] }
+
+WireDeclarations :: { [(Identifier, Maybe Expr)] }
+:                      WireDeclaration    { [$1] }
+| WireDeclarations "," WireDeclaration    { $1 ++ [$3] }
+
+WireDeclaration :: { (Identifier, Maybe Expr) }
+: Identifier               { [($1, Nothing)] }
+| Identifier "=" Expr      { [($1, Just $3)] }
 
 MaybeRange :: { Maybe Range }
 :         { Nothing }