Read and write the memory via a serial bridge

- drop the dedicated code_mem

BeMicro-CV/Makefile

@@ -21,7 +21,7 @@ bemicrocv.sta.summary: bemicrocv.fit.summary
 	@echo TIMING ANALYSING
 	@quartus_sta bemicrocv $(POST)
 
-SRC=test_yarvi.v bemicrocv.v rs232.v $(COMMON)yarvi.v $(COMMON)rs232rx.v $(COMMON)rs232tx.v
+SRC=test_yarvi.v bemicrocv.v axi_uart.v $(COMMON)htif.v $(COMMON)yarvi_soc.v $(COMMON)yarvi.v $(COMMON)rs232rx.v $(COMMON)rs232tx.v
 
 hw.sim: $(SRC) Makefile $(COMMON)program.txt $(COMMON)mem0.txt $(COMMON)mem1.txt $(COMMON)mem2.txt $(COMMON)mem3.txt
 	iverilog -DSIMULATION $(VERB) -DINITDIR=\"$(COMMON)\" $(IOPTS) -o /tmp/yarvi $(SRC)

BeMicro-CV/axi_uart.v

@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+module axi_uart
+  ( input  wire        clk
+  , input  wire        reset
+
+  , input  wire        serial_in
+  , output wire        serial_out
+
+  , output wire        tx_ready
+  , input  wire        tx_valid
+  , input  wire  [7:0] tx_data
+
+  , input  wire        rx_ready
+  , output reg         rx_valid = 0
+  , output reg   [7:0] rx_data = 'h XX
+  );
+
+   parameter frequency = 50_000_000;
+   parameter bps       =    115_200;
+
+   /* Very minimal one-byte buffer */
+
+`ifdef __ICARUS__
+   assign      tx_ready = 1;
+`else
+   assign      tx_ready = !rs232tx_busy;
+`endif
+
+   wire        rs232tx_busy;
+   wire        rs232rx_valid;
+   wire [ 7:0] rs232rx_q;
+
+   rs232rx rs232rx
+     ( .clock		(clk)
+     , .serial_in	(serial_in)
+     , .valid     	(rs232rx_valid)
+     , .q		(rs232rx_q));
+   defparam
+     rs232rx.frequency  = frequency,
+     rs232rx.bps        = bps;
+
+   rs232tx rs232tx
+      ( .clock		(clk)
+      , .serial_out	(serial_out)
+      , .d		(tx_data)
+      , .we		(tx_valid & tx_ready)
+      , .busy		(rs232tx_busy));
+   defparam
+     rs232tx.frequency  = frequency,
+     rs232tx.bps        = bps;
+
+   parameter inputtext  = {`INITDIR,"input.txt"};
+   integer   file, ch;
+
+   always @(posedge clk) begin
+      if (rx_ready & rx_valid) begin
+         rx_valid <= 0;
+
+`ifdef __ICARUS__
+         $display("RS232 READ %x '%c'", rx_data, rx_data);
+         ch = $fgetc(file);
+         if (ch >= 0) begin
+            rx_valid <= 1;
+            rx_data <= ch;
+         end
+`endif
+      end
+
+      if (rs232rx_valid) begin
+         rx_valid <= 1;
+         rx_data <= rs232rx_q;
+      end
+   end
+
+`ifdef __ICARUS__
+   always @(posedge clk)
+      if (tx_ready & tx_valid)
+         $display("RS232 WROTE %x '%c'", tx_data, tx_data);
+
+   initial begin
+      file = $fopen(inputtext, "r");
+      #100
+      rx_valid = 1;
+   end
+`endif
+endmodule

BeMicro-CV/bemicrocv.v

@@ -7,66 +7,53 @@ module bemicrocv
    output        gpio1,
    input         gpio2);
 
-   assign        user_led_n = address[7:0];
-
-   wire          tx_busy;
-
-   wire   [ 7:0] rx_q;
-   wire          rx_valid;
-
-   wire   [29:0] address;
-   wire   [31:0] writedata;
-   wire          writeenable;
-   wire   [31:0] readdata;
-   wire          readenable;
-   wire   [ 3:0] byteena;
+   wire          clk = clk_50;
 
    reg           reset = 1;
    always @(posedge clk_50)
       reset <= 1'd0;
 
    wire          serial_out, serial_in;
 
-   assign gpio1 = serial_out;
+   assign gpio1     = serial_out;
    assign serial_in = gpio2;
 
-   yarvi yarvi
-     ( .clk             (clk_50)
+   wire        tx_ready;
+   wire        tx_valid;
+   wire  [7:0] tx_data;
+
+   wire        rx_ready;
+   wire        rx_valid;
+   wire  [7:0] rx_data;
+
+   axi_uart axi_uart
+     ( .clk             (clk)
      , .reset           (reset)
-     , .address         (address)
-     , .writeenable     (writeenable)
-     , .writedata       (writedata)
-     , .byteena         (byteena)
-     , .readenable      (readenable)
-     , .readdata        (readdata)
-     );
 
-   rs232 rs232
-     ( .clk             (clk_50)
-     , .serial_out      (serial_out)
-     , .serial_in       (serial_in)
+     , .tx_ready        (tx_ready)
+     , .tx_valid        (tx_valid)
+     , .tx_data         (tx_data)
 
-     , .address         (address[0])
-     , .writeenable     (writeenable & address[29])
-     , .writedata       (writedata)
-     , .readenable      (readenable  & address[29])
-     , .readdata        (readdata));
+     , .rx_ready        (rx_ready)
+     , .rx_valid        (rx_valid)
+     , .rx_data         (rx_data)
+     );
 
-   reg 		 readdatavalid = 0;
-   always @(posedge clk_50)
-      readdatavalid <= readenable && address[29];
+   yarvi_soc yarvi_soc
+     ( .clk             (clk)
 
-`ifdef NOTDEF
-   always @(posedge clk_50)
-      if (writeenable /* && address[29] */)
-	$display("IO write %8x/%d -> [%8x]", writedata, byteena, address * 4);
+     , .rx_ready        (rx_ready)
+     , .rx_valid        (rx_valid)
+     , .rx_data         (rx_data)
 
-   always @(posedge clk_50)
-      if (readenable /* && address[29] */)
-	$display("IO read from [%8x]", writedata, byteena, address * 4);
+     , .tx_ready        (tx_ready)
+     , .tx_valid        (tx_valid)
+     , .tx_data         (tx_data)
+     );
 
-   always @(posedge clk_50)
-      if (readdatavalid)
-	$display("IO read -> %8x", readdata);
-`endif
+   initial begin
+      $dumpfile("test.vcd");
+      $dumpvars(0,bemicrocv);
+      #1000 $finish;
+   end
 endmodule

BeMicro-CV/rs232.v

@@ -1,6 +1,6 @@
 // -----------------------------------------------------------------------
 //
-//   Copyright 2014 Tommy Thorn - All Rights Reserved
+//   Copyright 2015 Tommy Thorn - All Rights Reserved
 //
 //   This program is free software; you can redistribute it and/or modify
 //   it under the terms of the GNU General Public License as published by

XuLA2/axi_uart.v

@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//**********************************************************************
+// The Xess JTAG UART with a AXI-like interface
+//**********************************************************************
+module axi_uart( input  wire        clk
+               , input  wire        reset
+
+               , output wire        tx_ready
+               , input  wire        tx_valid
+               , input  wire  [7:0] tx_data
+
+               , input  wire        rx_ready
+               , output wire        rx_valid
+               , output wire  [7:0] rx_data
+               );
+
+  wire       rx_empty;
+  reg        rx_pop = 0;
+
+  wire       tx_full;
+  reg        tx_add = 0;
+  reg [7:0]  tx_data_r;
+
+  // Instantiate the communication interface.
+  HostIoComm u2(
+    .reset_i    (reset),
+    .clk_i      (clk),
+
+    .rmv_i      (rx_pop),   // Remove data received from the host.
+    .data_o     (rx_data),  // Data from the host.
+    .dnEmpty_o  (rx_empty),
+
+    .add_i      (tx_add),   // Add received data to FIFO going back to host
+    .data_i     (tx_data_r),  // Data to host.
+    .upFull_o   (tx_full)
+    );
+  defparam u2.SIMPLE_G = 1;
+
+  assign     rx_valid = !rx_empty & !rx_pop;
+  assign     tx_ready = !tx_full  & !tx_add;
+
+  always @(posedge clk) begin
+    rx_pop <= rx_ready & rx_valid;
+    tx_add <= tx_ready & tx_valid;
+    tx_data_r <= tx_data;
+  end
+endmodule