Arm64 disassem shifted reg ror tests

sys/arm64/arm64/disassem.c

@@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
 #define	OP_RT_SP	(1UL << 8)	/* Use sp for RT otherwise xzr */
 #define	OP_RN_SP	(1UL << 9)	/* Use sp for RN otherwise xzr */
 #define	OP_RM_SP	(1UL << 10)	/* Use sp for RM otherwise xzr */
+#define	OP_SHIFT_ROR	(1UL << 11)	/* Use ror shift type */
 
 static const char *w_reg[] = {
 	"w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
@@ -69,7 +70,7 @@ static const char *x_reg[] = {
 };
 
 static const char *shift_2[] = {
-	"lsl", "lsr", "asr", "rsv"
+	"lsl", "lsr", "asr", "ror"
 };
 
 /*
@@ -232,6 +233,28 @@ static struct arm64_insn arm64_i[] = {
 	    TYPE_01, 0 },			/* negs shifted register */
 	{ "subs", "SF(1)|1101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)",
 	    TYPE_01, 0 },			/* subs shifted register */
+	{ "mvn", "SF(1)|0101010|SHIFT(2)|1|RM(5)|IMM(6)|11111|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* mvn shifted register */
+	{ "orn", "SF(1)|0101010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* orn shifted register */
+	{ "mov", "SF(1)|0101010000|RM(5)|000000|11111|RD(5)",
+	    TYPE_01, 0 },			/* mov register */
+	{ "orr", "SF(1)|0101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* orr shifted register */
+	{ "and", "SF(1)|0001010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* and shifted register */
+	{ "tst", "SF(1)|1101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|11111",
+	    TYPE_01, OP_SHIFT_ROR },		/* tst shifted register */
+	{ "ands", "SF(1)|1101010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* ands shifted register */
+	{ "bic", "SF(1)|0001010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* bic shifted register */
+	{ "bics", "SF(1)|1101010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* bics shifted register */
+	{ "eon", "SF(1)|1001010|SHIFT(2)|1|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* eon shifted register */
+	{ "eor", "SF(1)|1001010|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)",
+	    TYPE_01, OP_SHIFT_ROR },		/* eor shifted register */
 	{ NULL, NULL }
 };
 
@@ -420,6 +443,8 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt)
 	int pre;
 	/* Indicate if x31 register should be printed as sp or xzr */
 	int rm_sp, rt_sp, rd_sp, rn_sp;
+	/* Indicate if shift type ror is supported */
+	bool has_shift_ror;
 
 	/* Initialize defaults, all are 0 except SF indicating 64bit access */
 	shift = rd = rm = rn = imm = idx = option = amount = scale = 0;
@@ -464,6 +489,8 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt)
 	rd_sp = i_ptr->special_ops & OP_RD_SP;
 	rn_sp = i_ptr->special_ops & OP_RN_SP;
 
+	has_shift_ror = i_ptr->special_ops & OP_SHIFT_ROR;
+
 	/* Print opcode by type */
 	switch (i_ptr->type) {
 	case TYPE_01:
@@ -479,6 +506,13 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt)
 		rm_absent = arm64_disasm_read_token(i_ptr, insn, "RM", &rm);
 		arm64_disasm_read_token(i_ptr, insn, "SHIFT", &shift);
 
+		/*
+		 * if shift type is RESERVED for shifted register instruction,
+		 * print undefined
+		 */
+		if (shift == 3 && !has_shift_ror)
+			goto undefined;
+
 		di->di_printf("%s\t", i_ptr->name);
 
 		/*

sys/arm64/arm64/memcpy.S

@@ -240,3 +240,221 @@ L(copy64_from_start):
 END(memcpy)
 EEND(memmove)
 
+ENTRY(disasm_str_test)
+	/* str immediate post-index */
+	str	w0, [x3], #-256
+	str	w1, [sp], #255
+
+	str	x2, [x4], #1
+	str	x0, [sp], #-1
+
+	/* str immedate pre-index */
+	str	w0, [x3, #-256]!
+	str	w1, [sp, #255]!
+
+	str	x2, [x4, #1]
+	str	x0, [sp, #-1]
+
+	/* str immediate unsigned offset */
+	str	w0, [x3]
+	str	w0, [x3, #16380]
+	str	w1, [sp, #16380]
+
+	str	x0, [x3]
+	str	x2, [x3, #32760]
+	str	x3, [sp, #32760]
+
+	/* str register */
+	str	w0, [x1, x2, lsl #2]
+	str	w0, [x1, w2, uxtw #2]
+	str	w0, [sp, w2, sxtw]
+	str	w0, [sp, x2, sxtx #0]
+
+	str	x0, [x1, x2, lsl #3]
+	str	x0, [x1, w2, uxtw #3]
+	str	x0, [sp, w2, sxtw]
+	str	x0, [sp, x2, sxtx #0]
+
+	/* strb immediate post-index */
+	strb	w0, [x3], #-256
+	strb	w1, [sp], #255
+
+	/* strb immediate pre-index */
+	strb	w0, [x3, #-256]!
+	strb	w1, [sp, #255]!
+
+	/* strb immediate unsigned offset */
+	strb	w0, [x3]
+	strb	w0, [x3, #4095]
+	strb	w1, [sp, #4095]
+
+	/* strb register */
+	strb	w0, [x1, x2, sxtx #0]
+	strb	w0, [x1, x2, lsl #0]
+	strb	w0, [x1, w2, uxtw]
+	strb	w0, [sp, w2, sxtw]
+	strb	w0, [sp, x2, sxtx]
+
+	/* strh immediate post-index */
+	strh	w0, [x3], #-256
+	strh	w1, [sp], #255
+
+	/* strh immediate pre-index */
+	strh	w0, [x3, #-256]!
+	strh	w1, [sp, #255]!
+
+	/* strh immediate unsigned offset */
+	strh	w0, [x3]
+	strh	w0, [x3, #8190]
+	strh	w1, [sp, #8190]
+	strh	wzr, [sp, #8190]
+
+	/* strh register */
+	strh	w0, [x1, w2, uxtw #1]
+	strh	w0, [x1, x2, lsl #1]
+	strh	w0, [sp, w2, sxtw]
+	strh	w0, [sp, x2, sxtx #0]
+	strh	wzr, [sp, x2, sxtx #0]
+END(disasm_str_test)
+
+.macro ADDS_SHIFT_RSV_64 xd, xn, xm, shift, imm
+	.inst	((0b10101011 << 24) | (\shift << 22) | \
+		(0b0 << 21) 	    | (\xm << 16)    | \
+		(\imm << 10)	    | (\xn << 5)     | \
+		(\xd << 0))
+.endm
+
+ENTRY(disasm_shifted_reg_with_rsv)
+	/* adds shifted regiser */
+	adds	w0, w1, w3, asr #1
+	adds	x0, x1, x2, lsl #2
+
+	# adds	w0, w1, w3, RESERVED #1
+	ADDS_SHIFT_RSV_64 0, 1, 3, 3, 1
+
+	/* cmn shifted register, alias of adds */
+	cmn	w0, w4, lsr #31
+	cmn	x1, x10, asr #63
+
+	/* subs shifted register */
+	subs	w0, w11, w12, lsr #0
+	subs	x1, x12, x11, lsl #63
+
+	/* cmp shifted register, alias of subs */
+	cmp	w0, w1, asr #31
+	cmp	x0, x2, lsl #63
+
+	/* negs shifted register, alias of subs */
+	negs	w0, w1, lsr #31
+	negs	x0, x20, asr #0
+
+	/* sub shifted register */
+	sub	w0, w1, w2, lsl #1
+	sub	x0, x2, x1, lsl #5
+
+	/* neg shifted register */
+	neg	w0, w1, lsl #2
+	neg	x2, x3, asr #8
+END(disasm_shifted_reg_with_rsv)
+
+ENTRY(disasm_shifted_reg_with_ror)
+	/* mvn shifted register */
+	mvn	w0, w1
+	mvn	x0, x1
+
+	mvn	w0, w1, ror #3
+	mvn	x0, x1, ror #2
+
+	mvn	w0, wzr, asr #2
+	mvn	x0, xzr, lsl #1
+
+	/* orn shifted register */
+	orn	w0, wzr, w1
+	orn	x0, xzr, x1
+
+	orn	w0, w1, w2, ror #3
+	orn	x0, x1, x2, ror #2
+
+	orn	w0, w2, wzr, asr #2
+	orn	x0, x2, xzr, lsr #2
+
+	/* orr shifted register */
+	orr	w0, wzr, w1
+	orr	x0, xzr, x1
+
+	orr	w0, w1, w2, ror #3
+	orr	x0, x1, x2, ror #2
+
+	orr	w0, w2, wzr, asr #2
+	orr	x0, x2, xzr, lsr #2
+
+	/* and shifted register */
+	and	w0, wzr, w1
+	and	x0, xzr, x1
+
+	and	w0, w1, w2, ror #3
+	and	x0, x1, x2, ror #2
+
+	and	w0, w2, wzr, asr #2
+	and	x0, x2, xzr, lsr #2
+
+	/* ands shifted register */
+	ands	w0, wzr, w1
+	ands	x0, xzr, x1
+
+	ands	w0, w1, w2, ror #3
+	ands	x0, x1, x2, ror #2
+
+	ands	w0, w2, wzr, asr #2
+	ands	x0, x2, xzr, lsr #2
+
+	/* bic shifted register */
+	bic	w0, wzr, w1
+	bic	x0, xzr, x1
+
+	bic	w0, w1, w2, ror #3
+	bic	x0, x1, x2, ror #2
+
+	bic	w0, w2, wzr, asr #2
+	bic	x0, x2, xzr, lsr #2
+
+	/* bics shifted register */
+	bics	w0, wzr, w1
+	bics	x0, xzr, x1
+
+	bics	w0, w1, w2, ror #3
+	bics	x0, x1, x2, ror #2
+
+	bics	w0, w2, wzr, asr #2
+	bics	x0, x2, xzr, lsr #2
+
+	/* eon shifted register */
+	eon	w0, wzr, w1
+	eon	x0, xzr, x1
+
+	eon	w0, w1, w2, ror #3
+	eon	x0, x1, x2, ror #2
+
+	eon	w0, w2, wzr, asr #2
+	eon	x0, x2, xzr, lsr #2
+
+	/* eor shifted register */
+	eor	w0, wzr, w1
+	eor	x0, xzr, x1
+
+	eor	w0, w1, w2, ror #3
+	eor	x0, x1, x2, ror #2
+
+	eor	w0, w2, wzr, asr #2
+	eor	x0, x2, xzr, lsr #2
+
+	/* tst shifted register */
+	tst	w0, w1
+	tst	x0, x1
+
+	tst	w0, w1, ror #3
+	tst	x0, x1, ror #2
+
+	tst	w0, wzr, asr #2
+	tst	x0, xzr, lsl #1
+END(disasm_shifter_reg_with_ror)

sys/arm64/conf/RPI4

@@ -0,0 +1,46 @@
+#
+# GENERIC -- Generic kernel configuration file for FreeBSD/arm64
+#
+# For more information on this file, please read the config(5) manual page,
+# and/or the handbook section on Kernel Configuration Files:
+#
+#    https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+
+cpu		ARM64
+ident		RPI4
+
+include		"std.arm64"
+include		"std.dev"
+
+# Include SoC specific configuration
+include		"std.al"
+include		"std.allwinner"
+include		"std.altera"
+include		"std.amd"
+include		"std.arm"
+include		"std.broadcom"
+include		"std.cavium"
+include		"std.ec2"
+include		"std.hyperv"
+include		"std.hisilicon"
+include		"std.imx"
+include		"std.marvell"
+include		"std.nvidia"
+include		"std.nxp"
+include		"std.qcom"
+include		"std.rockchip"
+include		"std.virt"
+include		"std.xilinx"
+
+options		KDB