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Arm64 disassem shifted reg ror tests #2

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Arm64 disassem shifted reg ror tests #2

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Commits on May 28, 2023

  1. arm64/disassem.c: Add shifted register definitions with ror 

    Add disassembly support for the following shifted register instructions:
* mvn
* orn
* orr
* and
* ands
* bic
* bics
* eon
* eor
* tst

According to Arm64 documenation, operational pseuducode of shifted
register instruction must return `UNDEFINED` if shift type is `RESERVED`
('11'). Hence, removed "rsv" from `shift_2` array and added "ror".
In case of shift type is 4 and this type is `RESERVED`,
we will return `undefined`.
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    toor1245 committed May 28, 2023
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  2. add config RPI4

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    toor1245 committed May 28, 2023
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Commits on Jun 1, 2023

  1. arm64/disassem.c: add shifted regs with ror tests

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    toor1245 committed Jun 1, 2023
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Commits on Jun 10, 2023

  1. arm64/disassem.c change is_shift_ror to has_shift_ror and fix check 

    Changed is_shift_ror to has_shift_ror and fixed check when shift type is
3 (0b11), print undefined

Differential Revision: https://reviews.freebsd.org/D40386
    @toor1245
    toor1245 committed Jun 10, 2023
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Commits on Jun 11, 2023

  1. add inst with rsv

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    toor1245 committed Jun 11, 2023
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