This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.
opensource
verification
synthesis
gds
cts
netlist
placement
klayout
floorplan
openlane
openlane-flow
openlane-github-
netlist-simulation-
-
Updated
Mar 8, 2024 - Verilog