Exercício 02 de SystemVerilog
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Updated
Dec 8, 2016 - SystemVerilog
Exercício 02 de SystemVerilog
Execício 1 de SystemVerilog
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
MD5 hash generator
Simple UVM phase jumping
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