FPGA project source code to interface HDMI Receiver with SX3 with DDR based frame buffer implementation to support resolutions of up to 4K 30fps.
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Updated
Apr 4, 2021 - Verilog
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non-mtb-2-x
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FPGA project source code to interface HDMI Receiver with SX3 without frame buffer implementation to support video resolutions of up to 1080p 60fps.
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Updated
Apr 4, 2021 - Verilog
FPGA source code that can be used to test SX3 data parts (CYUSB3015 / CYUSB3016). Three modes are supported. 1- IN only, 2- OUT only, 3- IN + OUT only
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Updated
Apr 4, 2021 - Verilog
FPGA source code that generates single-tone sine wave audio data and colorbar for video resolution with height and width configurable through I2C interface. This test project can be used to validate FPGA to SX3 interface without dependency on HDMI Receiver interface. This FPGA project can be used to test UVC only, UAC only, UVC+UAC configurations.
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Updated
Apr 4, 2021 - Verilog
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