Design rule checker for VLSI layouts
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Updated
Jun 21, 2024 - C++
Design rule checker for VLSI layouts
A customized placer based on the RePlAce global placement tool.
Coursework of NTHU CS613500 VLSI Physical Design Automation
A SAT-Based cell router.
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
Steiner Shallow-Light Tree for VLSI Routing
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
VLSI EDA Global Router
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
Deep learning toolkit-enabled VLSI placement
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