Add AssertOn check for assert

Insert the check AssertOn to allow disabling of asserts.
Asserts can be disabled by not using the `--assert` flag and by setting
`AssertOn(false)`.
Add tests for this behavior.

Fixes verilator#2162.

Signed-off-by: Tobias Wölfel <tobias.woelfel@mailbox.org>

Changes

@@ -5,6 +5,7 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 4.029 devel
 
+***   Add assertOn check for assert [Tobias Wölfel]
 
 * Verilator 4.028 2020-02-08
 

docs/CONTRIBUTORS

@@ -33,6 +33,7 @@ Richard Myers
 Sebastien Van Cauwenberghe
 Stefan Wallentowitz
 Tobias Rosenkranz
+Tobias Wölfel
 Todd Strader
 Wilson Snyder
 Yutetsu TAKATSUKASA

src/V3Assert.cpp

@@ -150,7 +150,7 @@ class AssertVisitor : public AstNVisitor {
             // It's more LIKELY that we'll take the NULL if clause
             // than the sim-killing else clause:
             ifp->branchPred(VBranchPred::BP_LIKELY);
-            bodysp = ifp;
+            bodysp = newIfAssertOn(ifp);
         } else {
             nodep->v3fatalSrc("Unknown node type");
         }

test_regress/t/t_assert_disabled.pl

@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile();
+
+execute();
+
+ok(1);
+1;

test_regress/t/t_assert_disabled.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   always @ (posedge clk) begin
+      assert (0);
+      $finish();
+   end
+
+endmodule

test_regress/t/t_assert_enabled_bad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert'],
+    nc_flags2 => ['+assert'],
+    );
+
+execute(
+    fails => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_enabled_bad.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   always @ (posedge clk) begin
+      assert (0);
+      $finish;
+   end
+
+endmodule

test_regress/t/t_assert_enabled_off.cpp

@@ -0,0 +1,24 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+#include "Vt_assert_enabled_off.h"
+
+VM_PREFIX* top = NULL;
+
+double sc_time_stamp() { return (double)0; }
+
+int main(int argc, char* argv[]) {
+    top = new VM_PREFIX("top");
+    Verilated::debug(0);
+    Verilated::assertOn(false);
+
+    top->clk = 0;
+    top->eval();
+    top->clk = 1;
+    top->eval();
+
+}

test_regress/t/t_assert_enabled_off.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+compile(
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => ["--assert --exe $Self->{t_dir}/$Self->{name}.cpp"],
+    );
+
+execute();
+
+ok(1);
+1;

test_regress/t/t_assert_enabled_off.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   always @ (posedge clk) begin
+      assert (0);
+      $finish;
+   end
+
+endmodule

test_regress/t/t_assert_enabled_on_bad.cpp

@@ -0,0 +1,24 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+#include "Vt_assert_enabled_on_bad.h"
+
+VM_PREFIX* top = NULL;
+
+double sc_time_stamp() { return (double)0; }
+
+int main(int argc, char* argv[]) {
+    top = new VM_PREFIX("top");
+    Verilated::debug(0);
+    Verilated::assertOn(true);
+
+    top->clk = 0;
+    top->eval();
+    top->clk = 1;
+    top->eval();
+
+}

test_regress/t/t_assert_enabled_on_bad.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+compile(
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => ["--assert --exe $Self->{t_dir}/$Self->{name}.cpp"],
+    );
+
+execute(
+    fails => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_enabled_on_bad.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   always @ (posedge clk) begin
+      assert (0);
+      $finish;
+   end
+
+endmodule