FBU-RISC-V-DESIGN Within the scope of the project, the Instruction Decoder and ALU modules of a RISC-V processor, whose basic lines have been created before, will be designed and verified on the processor by using the SystemVerilog language features. The aim of the project is to learn and apply the design, working principle, receiving and using commands of a RISC-V based processor.

Turkish presentation link: youtube.com/watch?v=REiDWJjkDaE