This code is maintained by Angie. Let me know if you have any questions/feedback!
Copyright (c) 2015 - 2018 The Regents of the University of California. Released under the Modified (3-clause) BSD license.
Branches with code used in specific tapeouts are indicated below. Please cite relevant papers if you reference or use aspects of this repo in your work. :)
Generator Overview: "A generator of memory-based, runtime-reconfigurable 2n3m5k FFT engines" (ICASSP'16)
Branch craft0: "A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET" (ASSCC'17) -- Note that this branch uses (deprecated) Chisel2 and (deprecated) ChiselDSP.
Branch craft1: "A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET" (ESSCIRC'18) -- Note that this branch uses custom versions of Chisel-related repos tracked here.
Branch dac: "ACED: A Hardware Library for Generating DSP Systems" (DAC'18) -- Note that this branch was used for some systems modeling work related to the ACED: dsptools repo.