Atry100T Harness missing implicit clock assignment

[bchetwynd]

Background Work

• Yes, I searched the mailing list
• Yes, I searched prior issues
• Yes, I searched the documentation

Chipyard Version and Hash

Release: 1.10.0

OS Setup

Ex: Output of uname -a + lsb_release -a + printenv + conda list
Linux xUbuntu-2004-br24169 5.15.0-83-generic #92-Ubuntu SMP Mon Aug 14 09:30:42 UTC 2023 x86_64 x86_64 x86_64 GNU/Linux

Distributor ID: Ubuntu
Description: Ubuntu 22.04.3 LTS
Release: 22.04
Codename: jammy

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

Current Behavior

MISO input not properly connected in generated verilog when PMOD SD card interface is instantiated.

Arty100THarness.sv snippet:
.custom_boot (_plusarg_reader_out), // @[PlusArg.scala:80:11] .reset_io (_harnessBinderReset_catcher_io_sync_reset), // @[ResetCatchAndSync.scala:39:28] .clock_uncore_clock (_dutWrangler_auto_out_0_clock), // @[Harness.scala:33:31] .spi_0_dq_0_i (1'h0), .spi_0_dq_1_i (1'h0), .spi_0_dq_2_i (1'h0), .spi_0_dq_3_i (1'h0), .uart_0_rxd (_bundleIn_0_rxd_a2b_b), // @[Util.scala:30:21] .gpio_0_pins_0_i_ival (_gpio_iobuf_O), // @[CustomOverlays.scala:33:25] .gpio_0_pins_0_i_po (1'h0), // @[LazyModule.scala:411:29]

Expected Behavior

Arty100THarness.sv snipper

.custom_boot (_plusarg_reader_out), // @[PlusArg.scala:80:11] .reset_io (_harnessBinderReset_catcher_io_sync_reset), // @[ResetCatchAndSync.scala:39:28] .clock_uncore_clock (_dutWrangler_auto_out_0_clock), // @[Harness.scala:33:31] .spi_0_dq_0_i (1'h0), // @[LazyModule.scala:411:29] .spi_0_dq_1_i (bundleIn_0_dq_1_i_REG_1), // @[SDIOOverlay.scala:19:31] .spi_0_dq_2_i (1'h0), // @[LazyModule.scala:411:29] .spi_0_dq_3_i (1'h0), // @[LazyModule.scala:411:29] .uart_0_rxd (_bundleIn_0_rxd_a2b_b), // @[Util.scala:30:21] .gpio_0_pins_0_i_ival (_gpio_iobuf_O), // @[CustomOverlays.scala:33:25] .gpio_0_pins_0_i_po (1'h0), // @[LazyModule.scala:411:29]

Other Information

Recommended fix. Add the following lines to ./fpga/src/main/scala/arty100t/Harness.scala:

def referenceClockFreqMHz = dutFreqMHz
def referenceClock = dutClock.in.head._1.clock
def referenceReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }

childClock := harnessBinderClock
childReset := harnessBinderReset

ddrOverlay.mig.module.clock := harnessBinderClock
ddrOverlay.mig.module.reset := harnessBinderReset
ddrBlockDuringReset.module.clock := harnessBinderClock
ddrBlockDuringReset.module.reset := harnessBinder