Merge pull request #51 from ucb-bar/onetrueliteral

Support onetrueliteral (and new width specifier).

src/main/scala/examples/Adder.scala

@@ -7,15 +7,15 @@ import chisel3.util._
 //A n-bit adder with carry in and carry out
 class Adder(val n:Int) extends Module {
   val io = IO(new Bundle {
-    val A    = Input(UInt(width=n))
-    val B    = Input(UInt(width=n))
-    val Cin  = Input(UInt(width=1))
-    val Sum  = Output(UInt(width=n))
-    val Cout = Output(UInt(width=1))
+    val A    = Input(UInt(n.W))
+    val B    = Input(UInt(n.W))
+    val Cin  = Input(UInt(1.W))
+    val Sum  = Output(UInt(n.W))
+    val Cout = Output(UInt(1.W))
   })
   //create a vector of FullAdders
   val FAs   = Vec.fill(n)(Module(new FullAdder()).io)
-  val carry = Wire(Vec(n+1, UInt(width = 1)))
+  val carry = Wire(Vec(n+1, UInt(1.W)))
   val sum   = Wire(Vec(n, Bool()))
 
   //first carry is the top level carry in

src/main/scala/examples/Adder4.scala

@@ -7,11 +7,11 @@ import chisel3.util._
 //A 4-bit adder with carry in and carry out
 class Adder4 extends Module {
   val io = IO(new Bundle {
-    val A    = Input(UInt(width=4))
-    val B    = Input(UInt(width=4))
-    val Cin  = Input(UInt(width=1))
-    val Sum  = Output(UInt(width=4))
-    val Cout = Output(UInt(width=1))
+    val A    = Input(UInt(4.W))
+    val B    = Input(UInt(4.W))
+    val Cin  = Input(UInt(1.W))
+    val Sum  = Output(UInt(4.W))
+    val Cout = Output(UInt(1.W))
   })
   //Adder for bit 0
   val Adder0 = Module(new FullAdder())

src/main/scala/examples/ByteSelector.scala

@@ -5,12 +5,12 @@ import chisel3._
 
 class ByteSelector extends Module {
   val io = IO(new Bundle {
-    val in     = Input(UInt(width=32))
-    val offset = Input(UInt(width=2))
-    val out    = Output(UInt(width=8))
+    val in     = Input(UInt(32.W))
+    val offset = Input(UInt(2.W))
+    val out    = Output(UInt(8.W))
   })
-  io.out := UInt(0, width=8)
-  when (io.offset === UInt(0, width=2)) {
+  io.out := 0.U(8.W)
+  when (io.offset === 0.U(2.W)) {
     io.out := io.in(7,0)
   } .elsewhen (io.offset === 1.U) {
     io.out := io.in(15,8)

src/main/scala/examples/Combinational.scala

@@ -5,9 +5,9 @@ import chisel3._
 
 class Combinational extends Module {
   val io = IO(new Bundle {
-    val x   = Input(UInt(width= 16))
-    val y   = Input(UInt(width= 16))
-    val z   = Output(UInt(width=16))
+    val x   = Input(UInt(16.W))
+    val y   = Input(UInt(16.W))
+    val z   = Output(UInt(16.W))
   })
   io.z := io.x + io.y
 }

src/main/scala/examples/Darken.scala

@@ -5,8 +5,8 @@ import chisel3._
 
 class Darken extends Module {
   val io = IO(new Bundle {
-    val in  = Input(UInt(width=8))
-    val out = Output(UInt(width=8))
+    val in  = Input(UInt(8.W))
+    val out = Output(UInt(8.W))
   })
 
   io.out := io.in << 1.U

src/main/scala/examples/EnableShiftRegister.scala

@@ -5,19 +5,19 @@ import chisel3._
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt(width=4))
+    val in    = Input(UInt(4.W))
     val shift = Input(Bool())
-    val out   = Output(UInt(width=4))
+    val out   = Output(UInt(4.W))
   })
   val r0 = Reg(UInt())
   val r1 = Reg(UInt())
   val r2 = Reg(UInt())
   val r3 = Reg(UInt())
   when(reset) {
-    r0 := UInt(0, 4)
-    r1 := UInt(0, 4)
-    r2 := UInt(0, 4)
-    r3 := UInt(0, 4)
+    r0 := 0.U(4.W)
+    r1 := 0.U(4.W)
+    r2 := 0.U(4.W)
+    r3 := 0.U(4.W)
   } .elsewhen(io.shift) {
     r0 := io.in
     r1 := r0

src/main/scala/examples/FullAdder.scala

@@ -5,11 +5,11 @@ import chisel3._
 
 class FullAdder extends Module {
   val io = IO(new Bundle {
-    val a    = Input(UInt(width=1))
-    val b    = Input(UInt(width=1))
-    val cin  = Input(UInt(width=1))
-    val sum  = Output(UInt(width=1))
-    val cout = Output(UInt(width=1))
+    val a    = Input(UInt(1.W))
+    val b    = Input(UInt(1.W))
+    val cin  = Input(UInt(1.W))
+    val sum  = Output(UInt(1.W))
+    val cout = Output(UInt(1.W))
   })
 
   // Generate the sum

src/main/scala/examples/Functionality.scala

@@ -5,9 +5,9 @@ import chisel3._
 
 class Functionality extends Module {
   val io = IO(new Bundle {
-    val x   = Input(UInt(width= 16))
-    val y   = Input(UInt(width= 16))
-    val z   = Output(UInt(width=16))
+    val x   = Input(UInt(16.W))
+    val y   = Input(UInt(16.W))
+    val z   = Output(UInt(16.W))
   })
   def clb(a: UInt, b: UInt, c: UInt, d: UInt) =
     (a & b) | (~c & d)

src/main/scala/examples/HiLoMultiplier.scala

@@ -6,10 +6,10 @@ import chisel3._
 //A 4-bit adder with carry in and carry out
 class HiLoMultiplier() extends Module {
   val io = IO(new Bundle {
-    val A  = Input(UInt(width=16))
-    val B  = Input(UInt(width=16))
-    val Hi = Output(UInt(width=16))
-    val Lo = Output(UInt(width=16))
+    val A  = Input(UInt(16.W))
+    val B  = Input(UInt(16.W))
+    val Hi = Output(UInt(16.W))
+    val Lo = Output(UInt(16.W))
   })
   val mult = io.A * io.B
   io.Lo := mult(15, 0)

src/main/scala/examples/Life.scala

@@ -10,16 +10,16 @@ class Cell(isBorn: Boolean) extends Module {
     val nbrs = Vec(8, Input(Bool()))
     val out  = Output(Bool())
   })
-  val isAlive = Reg(init=Bool(isBorn))
-  val count   = io.nbrs.foldRight(UInt(0, 3))((x: Bool, y: UInt) => x.asUInt + y)
+  val isAlive = Reg(init=isBorn.B)
+  val count   = io.nbrs.foldRight(0.U(3.W))((x: Bool, y: UInt) => x.asUInt + y)
   when (count < 2.U) {
-    isAlive := Bool(false)
+    isAlive := false.B
   } .elsewhen (count < 4.U) {
-    isAlive := Bool(true)
+    isAlive := true.B
   } .elsewhen (count >= 4.U) {
-    isAlive := Bool(false)
+    isAlive := false.B
   } .elsewhen(!isAlive && count === 3.U) {
-    isAlive := Bool(true)
+    isAlive := true.B
   }
   io.out := isAlive
 }

src/main/scala/examples/LogShifter.scala

@@ -5,30 +5,30 @@ import chisel3._
 
 class LogShifter extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt(width=16))
-    val shamt = Input(UInt(width=4))
-    val out   = Output(UInt(width=16))
+    val in    = Input(UInt(16.W))
+    val shamt = Input(UInt(4.W))
+    val out   = Output(UInt(16.W))
   })
-  val s0 = Reg(init = UInt(0, 16))
-  when (io.shamt(3) === UInt(1)) {
-    s0 := io.in << UInt(8)
+  val s0 = Reg(init = 0.U(16.W))
+  when (io.shamt(3) === 1.U) {
+    s0 := io.in << 8.U
   } .otherwise {
     s0 := io.in
   }
-  val s1 = Reg(init = UInt(0, 16))
-  when (io.shamt(2) === UInt(1)) {
-    s1 := s0 << UInt(4)
+  val s1 = Reg(init = 0.U(16.W))
+  when (io.shamt(2) === 1.U) {
+    s1 := s0 << 4.U
   } .otherwise {
     s1 := s0
   }
-  val s2 = Reg(init = UInt(0, 16))
-  when (io.shamt(1) === UInt(1)) {
-    s2 := s1 << UInt(2)
+  val s2 = Reg(init = 0.U(16.W))
+  when (io.shamt(1) === 1.U) {
+    s2 := s1 << 2.U
   } .otherwise {
     s2 := s1
   }
-  when (io.shamt(1) === UInt(1)) {
-    io.out := s2 << UInt(1)
+  when (io.shamt(1) === 1.U) {
+    io.out := s2 << 1.U
   } .otherwise {
     io.out := s2
   }

src/main/scala/examples/ResetShiftRegister.scala

@@ -5,15 +5,15 @@ import chisel3._
 
 class ResetShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt(width=4))
+    val in    = Input(UInt(4.W))
     val shift = Input(Bool())
-    val out   = Output(UInt(width=4))
+    val out   = Output(UInt(4.W))
   })
   // Register reset to zero
-  val r0 = Reg(init = UInt(0, width = 4))
-  val r1 = Reg(init = UInt(0, width = 4))
-  val r2 = Reg(init = UInt(0, width = 4))
-  val r3 = Reg(init = UInt(0, width = 4))
+  val r0 = Reg(init = 0.U(4.W))
+  val r1 = Reg(init = 0.U(4.W))
+  val r2 = Reg(init = 0.U(4.W))
+  val r3 = Reg(init = 0.U(4.W))
   when (io.shift) {
     r0 := io.in
     r1 := r0

src/main/scala/examples/Risc.scala

@@ -7,15 +7,15 @@ import chisel3.util._
 class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
-    val wrAddr = Input(UInt(width=8))
-    val wrData = Input(UInt(width=32))
+    val wrAddr = Input(UInt(8.W))
+    val wrData = Input(UInt(32.W))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
-    val out    = Output(UInt(width=32))
+    val out    = Output(UInt(32.W))
   })
-  val file = Mem(256, UInt(width = 32))
-  val code = Mem(256, UInt(width = 32))
-  val pc   = Reg(init=UInt(0, 8))
+  val file = Mem(256, UInt(32.W))
+  val code = Mem(256, UInt(32.W))
+  val pc   = Reg(init=0.U(8.W))
 
   val add_op :: imm_op :: Nil = Enum(UInt(), 2)
 
@@ -25,13 +25,13 @@ class Risc extends Module {
   val rai  = inst(15, 8)
   val rbi  = inst( 7, 0)
 
-  val ra = Mux(rai === UInt(0), UInt(0), file(rai))
-  val rb = Mux(rbi === UInt(0), UInt(0), file(rbi))
-  val rc = Wire(UInt(width = 32))
+  val ra = Mux(rai === 0.U, 0.U, file(rai))
+  val rb = Mux(rbi === 0.U, 0.U, file(rbi))
+  val rc = Wire(UInt(32.W))
 
-  io.valid := Bool(false)
-  io.out   := UInt(0)
-  rc       := UInt(0)
+  io.valid := false.B
+  io.out   := 0.U
+  rc       := 0.U
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
@@ -44,7 +44,7 @@ class Risc extends Module {
     }
     io.out := rc
     when (rci === 255.U) {
-      io.valid := Bool(true)
+      io.valid := true.B
     } .otherwise {
       file(rci) := rc
     }

src/main/scala/examples/ShiftRegister.scala

@@ -5,8 +5,8 @@ import chisel3._
 
 class ShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in  = Input(UInt(width= 1))
-    val out = Output(UInt(width=1))
+    val in  = Input(UInt(1.W))
+    val out = Output(UInt(1.W))
   })
   val r0 = Reg(next = io.in)
   val r1 = Reg(next = r0)

src/main/scala/examples/SimpleALU.scala

@@ -5,10 +5,10 @@ import chisel3._
 
 class BasicALU extends Module {
   val io = IO(new Bundle {
-    val a = Input(UInt(width=4))
-    val b = Input(UInt(width=4))
-    val opcode = Input(UInt(width=4))
-    val out = Output(UInt(width=4))
+    val a = Input(UInt(4.W))
+    val b = Input(UInt(4.W))
+    val opcode = Input(UInt(4.W))
+    val out = Output(UInt(4.W))
   })
   io.out := 0.U //THIS SEEMS LIKE A HACK/BUG
   when (io.opcode === 0.U) {
@@ -36,10 +36,10 @@ class BasicALU extends Module {
 
 class SimpleALU extends Module {
   val io = IO(new Bundle {
-    val a      = Input(UInt(width= 4))
-    val b      = Input(UInt(width= 4))
-    val opcode = Input(UInt(width= 2))
-    val out = Output(UInt(width=4))
+    val a      = Input(UInt(4.W))
+    val b      = Input(UInt(4.W))
+    val opcode = Input(UInt(2.W))
+    val out = Output(UInt(4.W))
   })
   io.out := 0.U
   when (io.opcode === 0.U) {

src/main/scala/examples/Stack.scala

@@ -13,16 +13,16 @@ class Stack(val depth: Int) extends Module {
     val push    = Input(Bool())
     val pop     = Input(Bool())
     val en      = Input(Bool())
-    val dataIn  = Input(UInt(width= 32))
-    val dataOut = Output(UInt(width=32))
+    val dataIn  = Input(UInt(32.W))
+    val dataOut = Output(UInt(32.W))
   })
 
-  val stack_mem = Mem(depth, UInt(width = 32))
-  val sp        = Reg(init = UInt(0, width = log2Up(depth+1)))
-  val out       = Reg(init = UInt(0, width = 32))
+  val stack_mem = Mem(depth, UInt(32.W))
+  val sp        = Reg(init = 0.U(log2Up(depth+1).W))
+  val out       = Reg(init = 0.U(32.W))
 
   when (io.en) {
-    when(io.push && (sp < UInt(depth))) {
+    when(io.push && (sp < depth.asUInt)) {
       stack_mem(sp) := io.dataIn
       sp := sp + 1.U
     } .elsewhen(io.pop && (sp > 0.U)) {

src/main/scala/examples/Tbl.scala

@@ -5,9 +5,9 @@ import chisel3._
 
 class Tbl extends Module {
   val io = IO(new Bundle {
-    val addr = Input(UInt(width= 8))
-    val out  = Output(UInt(width=8))
+    val addr = Input(UInt(8.W))
+    val out  = Output(UInt(8.W))
   })
-  val r = Wire(init = Vec(Range(0, 256).map(UInt(_, width = 8))))
+  val r = Wire(init = Vec(Range(0, 256).map(_.asUInt(8.W))))
   io.out := r(io.addr)
 }

src/main/scala/examples/VecSearch.scala

@@ -9,10 +9,10 @@ object VecSearchTest {
 
 class VecSearch extends Module {
   val io = IO(new Bundle {
-    val out = Output(UInt(width= 4))
+    val out = Output(UInt(4.W))
   })
-  val index = Reg(init = UInt(0, width = 3))
-  val elts  = Wire(init = Vec(VecSearchTest.pattern.map(UInt(_, 4))))
+  val index = Reg(init = 0.U(3.W))
+  val elts  = Wire(init = Vec(VecSearchTest.pattern.map(_.asUInt(4.W))))
   index := index + 1.U
   io.out := elts(index)
 }

src/main/scala/hello/Hello.scala

@@ -6,9 +6,9 @@ import chisel3.iotesters.{PeekPokeTester, Driver}
 
 class Hello extends Module {
   val io = IO(new Bundle {
-    val out = Output(UInt(width=8))
+    val out = Output(UInt(8.W))
   })
-  io.out := UInt(42)
+  io.out := 42.U
 }
 
 class HelloTests(c: Hello) extends PeekPokeTester(c) {