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Bulk connects do not override bundle components #699
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Does csr.io.rocc.resp.ready exist? Would a dead code elimination pass help with resolving this class of issue? |
I think a good solution (at least to help migration) would just be another chisel 3 compatibility warning/error when you do this. Any bulk connects to a bundle after any part of it has been assigned to (bulk or otherwise) will potentially hit this issue. I just ran into it again with something like the following.
In this case the module b only reads from its io.bundle but chisel3 generates an assign to io.bundle's outputs with b.io.bundle causing a random value to be assigned. |
It would be helpful to be able to specify inclusion/exclusion filters in the bulk connect. Something along the lines of
Ideally, the syntax would support wildcards/regex on the port/sub-bundle names, e.g.:
Besides solving double assignments with only the last-one-wins-rule, this would also facilitate literate programming in the sense of making connections more explicit. |
Bundle.elements: LinkedHashMap[String, Data] is already available. So users On Sat, Sep 3, 2016 at 12:02 AM, jkorinth notifications@github.com wrote:
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This code behaves differently in Chisel2 and 3. It would be good if the compatibility checker would catch it.
In Chisel2 because the csr module does not write to rocc.resp.ready the initial assignment is preserved and last connect semantics are ignored.
In Chisel3 last connect semantics are honored and the second bulk connect overrides the previous assignment. This leads to a random value since csr.io.rocc.resp.ready was never written to.
This anomalous behavior in Chisel2 can cause issues in porting from chisel2 to chisel3 as it silently generates a different circuit.
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