last change to Reg() prototype before pushing 2.0 out

src/main/scala/ChiselUtil.scala

@@ -61,7 +61,7 @@ object LFSR16
   def apply(increment: Bool = Bool(true)): UInt =
   {
     val width = 16
-    val lfsr = RegReset(UInt(1, width))
+    val lfsr = Reg(init=UInt(1, width))
     when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
     lfsr
   }
@@ -108,7 +108,7 @@ object RegEnable
     r
   }
   def apply[T <: Data](updateData: T, resetData: T, enable: Bool) = {
-    val r = RegReset(resetData)
+    val r = RegInit(resetData)
     when (enable) { r := updateData }
     r
   }
@@ -119,7 +119,7 @@ object ShiftRegister
   def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T =
   {
     if (n == 1) RegEnable(in, en)
-    else RegUpdate(apply(in, n-1, en))
+    else RegNext(apply(in, n-1, en))
   }
 }
 
@@ -242,8 +242,8 @@ object ArbiterCtrl
 abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) extends Module {
   require(isPow2(count))
   val io = new ArbiterIO(gen, n)
-  val locked  = if(count > 1) RegReset(Bool(false)) else Bool(false)
-  val lockIdx = if(count > 1) RegReset(UInt(n-1)) else UInt(n-1)
+  val locked  = if(count > 1) Reg(init=Bool(false)) else Bool(false)
+  val lockIdx = if(count > 1) Reg(init=UInt(n-1)) else UInt(n-1)
   val grant = List.fill(n)(Bool())
   val chosen = UInt(width = log2Up(n))
 
@@ -253,7 +253,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   io.chosen := chosen
 
   if(count > 1){
-    val cnt = RegReset(UInt(0, width = log2Up(count)))
+    val cnt = Reg(init=UInt(0, width = log2Up(count)))
     val cnt_next = cnt + UInt(1)
     when(io.out.fire()) {
       when(needsLock.map(_(io.out.bits)).getOrElse(Bool(true))) {
@@ -271,7 +271,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 }
 
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None) extends LockingArbiterLike[T](gen, n, count, needsLock) {
-  val last_grant = RegReset(UInt(0, log2Up(n)))
+  val last_grant = Reg(init=UInt(0, log2Up(n)))
   val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).valid && UInt(i) > last_grant) ++ io.in.map(_.valid))
   (0 until n).map(i => grant(i) := ctrl(i) && UInt(i) > last_grant || ctrl(i + n))
 
@@ -316,7 +316,7 @@ object FillInterleaved
 object Counter
 {
   def apply(cond: Bool, n: Int): (UInt, Bool) = {
-    val c = RegReset(UInt(0, log2Up(n)))
+    val c = Reg(init=UInt(0, log2Up(n)))
     val wrap = c === UInt(n-1)
     when (cond) {
       c := Mux(Bool(!isPow2(n)) && wrap, UInt(0), c + UInt(1))
@@ -348,7 +348,7 @@ class Queue[T <: Data](gen: T, val entries: Int, pipe: Boolean = false, flow: Bo
     deq_ptr = Counter(do_deq, entries)._1
   }
 
-  val maybe_full = RegReset(Bool(false))
+  val maybe_full = Reg(init=Bool(false))
   when (do_enq != do_deq) {
     maybe_full := do_enq
   }
@@ -389,27 +389,27 @@ class AsyncFifo[T<:Data](gen: T, entries: Int, enq_clk: Clock, deq_clk: Clock) e
   val io = new QueueIO(gen, entries)
   val asize = log2Up(entries)
 
-  val s1_rptr_gray = RegReset(UInt(0, asize+1)).withClock(enq_clk)
-  val s2_rptr_gray = RegReset(UInt(0, asize+1)).withClock(enq_clk)
-  val s1_rst_deq = RegReset(Bool(false)).withClock(enq_clk)
-  val s2_rst_deq = RegReset(Bool(false)).withClock(enq_clk)
+  val s1_rptr_gray = Reg(init=UInt(0, asize+1)).withClock(enq_clk)
+  val s2_rptr_gray = Reg(init=UInt(0, asize+1)).withClock(enq_clk)
+  val s1_rst_deq = Reg(init=Bool(false)).withClock(enq_clk)
+  val s2_rst_deq = Reg(init=Bool(false)).withClock(enq_clk)
 
-  val s1_wptr_gray = RegReset(UInt(0, asize+1)).withClock(deq_clk)
-  val s2_wptr_gray = RegReset(UInt(0, asize+1)).withClock(deq_clk)
-  val s1_rst_enq = RegReset(Bool(false)).withClock(deq_clk)
-  val s2_rst_enq = RegReset(Bool(false)).withClock(deq_clk)
+  val s1_wptr_gray = Reg(init=UInt(0, asize+1)).withClock(deq_clk)
+  val s2_wptr_gray = Reg(init=UInt(0, asize+1)).withClock(deq_clk)
+  val s1_rst_enq = Reg(init=Bool(false)).withClock(deq_clk)
+  val s2_rst_enq = Reg(init=Bool(false)).withClock(deq_clk)
 
-  val wptr_bin = RegReset(UInt(0, asize+1)).withClock(enq_clk)
-  val wptr_gray = RegReset(UInt(0, asize+1)).withClock(enq_clk)
-  val not_full = RegReset(Bool(false)).withClock(enq_clk)
+  val wptr_bin = Reg(init=UInt(0, asize+1)).withClock(enq_clk)
+  val wptr_gray = Reg(init=UInt(0, asize+1)).withClock(enq_clk)
+  val not_full = Reg(init=Bool(false)).withClock(enq_clk)
 
   val wptr_bin_next = wptr_bin + (io.enq.valid & not_full)
   val wptr_gray_next = (wptr_bin_next >> UInt(1)) ^ wptr_bin_next
   val not_full_next = !(wptr_gray_next === Cat(~s2_rptr_gray(asize,asize-1), s2_rptr_gray(asize-2,0)))
 
-  val rptr_bin = RegReset(UInt(0, asize+1)).withClock(deq_clk)
-  val rptr_gray = RegReset(UInt(0, asize+1)).withClock(deq_clk)
-  val not_empty = RegReset(Bool(false)).withClock(deq_clk)
+  val rptr_bin = Reg(init=UInt(0, asize+1)).withClock(deq_clk)
+  val rptr_gray = Reg(init=UInt(0, asize+1)).withClock(deq_clk)
+  val not_empty = Reg(init=Bool(false)).withClock(deq_clk)
 
   val rptr_bin_next = rptr_bin + (io.deq.ready & not_empty)
   val rptr_gray_next = (rptr_bin_next >> UInt(1)) ^ rptr_bin_next
@@ -480,7 +480,7 @@ object Pipe
       out.setIsTypeNode
       out
     } else {
-      val v = Reg(Bool(), updateData=enqValid, resetData=Bool(false))
+      val v = Reg(Bool(), next=enqValid, init=Bool(false))
       val b = RegEnable(enqBits, enqValid)
       apply(v, b, latency-1)
     }

src/main/scala/Cpp.scala

@@ -388,7 +388,7 @@ class CppBackend extends Backend {
           + i + ")"))
 
       case reg: Reg =>
-        def updateData(w: Int): String = if (reg.isReset) "TERNARY(" + emitLoWordRef(reg.inputs.last) + ", " + emitWordRef(reg.resetData, w) + ", " + emitWordRef(reg.updateData, w) + ")" else emitWordRef(reg.updateData, w)
+        def updateData(w: Int): String = if (reg.isReset) "TERNARY(" + emitLoWordRef(reg.inputs.last) + ", " + emitWordRef(reg.init, w) + ", " + emitWordRef(reg.next, w) + ")" else emitWordRef(reg.next, w)
 
         def shadow(w: Int): String = emitRef(reg) + "_shadow.values[" + w + "]"
         block((0 until words(reg)).map(i => shadow(i) + " = " + updateData(i)))

src/main/scala/Flo.scala

@@ -132,7 +132,7 @@ class FloBackend extends Backend {
         emitDec(m) + "st " + emitRef(m.mem) + " " + emitRef(m.addr) + " " + emitRef(m.data) + "\n"
 
       case x: Reg => // TODO: need resetData treatment
-        emitDec(x) + "reg " + emitRef(x.updateData) + "\n"
+        emitDec(x) + "reg " + emitRef(x.next) + "\n"
 
       case x: Log2 => // TODO: log2 instruction?
         emitDec(x) + "log2/" + x.width + " " + emitRef(x.inputs(0)) + "\n"

src/main/scala/Mem.scala

@@ -117,10 +117,10 @@ class Mem[T <: Data](gen: () => T, val n: Int, val seqRead: Boolean) extends Acc
       // generate bogus data when reading & writing same address on same cycle
       val reg_data = Reg(gen())
       reg_data.comp procAssign wdata
-      val reg_wmask = if (wmask == null) null else Reg(updateData=wmask)
+      val reg_wmask = if (wmask == null) null else Reg(next=wmask)
       val random16 = LFSR16()
       val random_data = Cat(random16, Array.fill((width-1)/16){random16}:_*)
-      doit(Reg(updateData=addr), Reg(updateData=cond), reg_data, reg_wmask)
+      doit(Reg(next=addr), Reg(next=cond), reg_data, reg_wmask)
       doit(addr, cond, gen().fromNode(random_data), wmask)
       reg_data.comp
     } else {
@@ -198,7 +198,7 @@ class MemSeqRead(mem: Mem[_], addri: Node) extends MemAccess(mem, addri) {
   override def addr = if(inputs.length > 2) inputs(2) else null
 
   override def forceMatchingWidths = {
-    val forced = addrReg.updateData.matchWidth(log2Up(mem.n))
+    val forced = addrReg.next.matchWidth(log2Up(mem.n))
     inputs += forced
     assert(addr == forced)
   }

src/main/scala/Reg.scala

@@ -77,13 +77,13 @@ object Reg {
     *update* and *reset* define the update and reset values
     respectively.
     */
-  def apply[T <: Data](outType: T = null, updateData: T = null, resetData: T = null): T = {
+  def apply[T <: Data](outType: T = null, next: T = null, init: T = null): T = {
     var mType = outType
     if(mType == null) {
-      mType = updateData
+      mType = next
     }
     if(mType == null) {
-      mType = resetData
+      mType = init
     }
     if(mType == null) {
       throw new Exception("cannot infer type of Reg.")
@@ -93,17 +93,17 @@ object Reg {
     validateGen(gen)
 
     val d: Array[(String, Bits)] =
-      if(updateData == null) {
+      if(next == null) {
         gen.flatten.map{case(x, y) => (x -> null)}
       } else {
-        updateData.flatten
+        next.flatten
       }
 
     // asOutput flip the direction and returns this.
     val res = gen.asOutput
 
-    if(resetData != null) {
-      for((((res_n, res_i), (data_n, data_i)), (rval_n, rval_i)) <- res.flatten zip d zip resetData.flatten) {
+    if(init != null) {
+      for((((res_n, res_i), (data_n, data_i)), (rval_n, rval_i)) <- res.flatten zip d zip init.flatten) {
 
         assert(rval_i.getWidth > 0,
           {ChiselError.error("Negative width to wire " + res_i)})
@@ -136,28 +136,30 @@ object Reg {
   def apply[T <: Data](outType: T): T = Reg[T](outType, null.asInstanceOf[T], null.asInstanceOf[T])
 }
 
-object RegUpdate {
 
-  def apply[T <: Data](updateData: T): T = Reg[T](updateData, updateData, null.asInstanceOf[T])
+object RegNext {
 
-  def apply[T <: Data](updateData: T, resetData: T): T = Reg[T](updateData, updateData, resetData)
+  def apply[T <: Data](next: T): T = Reg[T](next, next, null.asInstanceOf[T])
+
+  def apply[T <: Data](next: T, init: T): T = Reg[T](next, next, init)
 
 }
 
-object RegReset {
+object RegInit {
 
-  def apply[T <: Data](resetData: T): T = Reg[T](resetData, null.asInstanceOf[T], resetData)
+  def apply[T <: Data](init: T): T = Reg[T](init, null.asInstanceOf[T], init)
 
 }
 
+
 class Reg extends Delay with proc {
-  def updateData: Node = inputs(0);
-  def resetData: Node  = inputs(1);
+  def next: Node = inputs(0);
+  def init: Node  = inputs(1);
   def enableSignal: Node = inputs(enableIndex);
   var enableIndex = 0;
   var isReset = false
   var isEnable = false;
-  def isUpdate: Boolean = !(updateData == null);
+  def isUpdate: Boolean = !(next == null);
   def update (x: Node) { inputs(0) = x };
   var assigned = false;
   var enable = Bool(false);

src/main/scala/Verilog.scala

@@ -568,22 +568,22 @@ class VerilogBackend extends Backend {
         } else if(reg.isEnable && (reg.enableSignal.litOf == null || reg.enableSignal.litOf.value != 1)){
           if(reg.isReset){
             "    if(" + emitRef(reg.inputs.last) + ") begin\n" +
-            "      " + emitRef(reg) + " <= " + emitRef(reg.resetData) + ";\n" +
+            "      " + emitRef(reg) + " <= " + emitRef(reg.init) + ";\n" +
             "    end else if(" + emitRef(reg.enableSignal) + ") begin\n" +
-            "      " + emitRef(reg) + " <= " + emitRef(reg.updateData) + ";\n" +
+            "      " + emitRef(reg) + " <= " + emitRef(reg.next) + ";\n" +
             "    end\n"
           } else {
             "    if(" + emitRef(reg.enableSignal) + ") begin\n" +
-            "      " + emitRef(reg) + " <= " + emitRef(reg.updateData) + ";\n" +
+            "      " + emitRef(reg) + " <= " + emitRef(reg.next) + ";\n" +
             "    end\n"
           }
         } else {
           "    " + emitRef(reg) + " <= " +
           (if (reg.isReset) {
-            emitRef(reg.inputs.last) + " ? " + emitRef(reg.resetData) + " : "
+            emitRef(reg.inputs.last) + " ? " + emitRef(reg.init) + " : "
           } else {
             ""
-          }) + emitRef(reg.updateData) + ";\n"
+          }) + emitRef(reg.next) + ";\n"
         }
 
       case m: MemWrite =>

src/test/scala/DotBackendTest.scala

@@ -70,7 +70,7 @@ class DotBackendSuite extends AssertionsForJUnit {
         val ready = Bool(INPUT)
         val valid = Bool(OUTPUT)
       }
-      val stored = Reg(updateData=io.ready)
+      val stored = Reg(next=io.ready)
       io.valid := stored
     }
 

src/test/scala/NameTest.scala

@@ -630,7 +630,7 @@ endmodule
       }
 
       io.mem := io.requestor(0).req.ready
-      val r_valid = io.requestor.map(r => Reg(updateData=r.req.ready))
+      val r_valid = io.requestor.map(r => Reg(next=r.req.ready))
 
       for(i <- 0 to 3) {
         when (r_valid(i)) {
@@ -831,7 +831,7 @@ endmodule
         val ctrl_out = Bool(OUTPUT);
       }
       // writeback definitions
-      val wb_reg_ll_wb          = Reg(resetData=Bool(false));
+      val wb_reg_ll_wb          = Reg(init=Bool(false));
       val wb_wen = io.ctrl_wb_wen || wb_reg_ll_wb
 
       when (wb_wen) { wb_reg_ll_wb := io.ctrl_wb_wen }

src/test/scala/VerifTest.scala

@@ -173,7 +173,7 @@ void VerifSuite_CppPrintfComp_1_t::dump(FILE *f, int t) {
         val z = UInt(OUTPUT)
       }
 
-      val tsc_reg = Reg(resetData=UInt(0, width=32))
+      val tsc_reg = Reg(init=UInt(0, width=32))
       tsc_reg := tsc_reg + UInt(1/*, width=32*/)
 
       printf("Cyc= %d io: %x %x", tsc_reg(31,0), io.x, io.y)