Merge pull request #34 from ucb-bar/scala213

Bump to scala 2.13

.github/workflows/ci.yml

@@ -36,7 +36,7 @@ jobs:
         git submodule update --init --recursive
         git clone https://github.com/chipsalliance/rocket-chip.git
         cd rocket-chip
-        git checkout 045d03c54bce7636401b1b4b17d6a3677356dfe0
+        git checkout 3b5fb3c043ccc2cea81ed7a44b295f4652d0ba02
         git submodule update --init --recursive
         sbt "publishLocal"
         sbt "project api-config-chipsalliance; set publishArtifact := true; publishLocal"

build.sbt

@@ -1,9 +1,8 @@
 name := "constellation"
 version := "0.1"
-scalaVersion := "2.12.12"
+scalaVersion := "2.13.10"
 
 scalacOptions ++= Seq(
-  "-Xsource:2.11",
   "-language:reflectiveCalls",
   "-deprecation",
   "-feature"
@@ -14,17 +13,17 @@ val standalone = sys.env.get("CONSTELLATION_STANDALONE").isDefined
 // SNAPSHOT repositories
 libraryDependencies ++= (if (standalone) {
   Seq(
-    "edu.berkeley.cs" %% "rocketchip" % "1.2-SNAPSHOT",
-    "edu.berkeley.cs" %% "api-config-chipsalliance" % "1.2-SNAPSHOT",
-    "edu.berkeley.cs" %% "rocket-macros" % "1.2-SNAPSHOT",
+    "edu.berkeley.cs" %% "rocketchip" % "1.6.0",
+    "edu.berkeley.cs" %% "api-config-chipsalliance" % "1.6.0",
+    "edu.berkeley.cs" %% "rocket-macros" % "1.6.0",
     "edu.berkeley.cs" %% "chiseltest" % "0.5.4" % "test"
   )
 } else {
   Nil
 })
 
 addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin"
-  % (if (standalone) "3.5.2" else "3.5.1") cross CrossVersion.full)
+  % (if (standalone) "3.5.5" else "3.5.5") cross CrossVersion.full)
 
 import Tests._
 

docs/source/Introduction/Installation.rst

@@ -44,7 +44,7 @@ For a **Minimal-Standalone** installation, Rocketchip must be manually installed
 
    git clone https://github.com/chipsalliance/rocket-chip.git
    cd rocket-chip
-   git checkout 045d03c54bce7636401b1b4b17d6a3677356dfe0
+   git checkout 3b5fb3c043ccc2cea81ed7a44b295f4652d0ba02
    git submodule update --init --recursive
    sbt "publishLocal"
    sbt "project api-config-chipsalliance; set publishArtifact := true; publishLocal"

src/main/scala/noc/NoC.scala

@@ -79,8 +79,8 @@ class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
     val routerI = routers.find(_.nodeId == i)
     val routerJ = routers.find(_.nodeId == j)
     if (routerI.isDefined && routerJ.isDefined) {
-      val sourceNodes = routerI.get.sourceNodes.find(_.destId == j)
-      val destNodes = routerJ.get.destNodes.filter(_.destParams.srcId == i)
+      val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
+      val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
       require (sourceNodes.size == destNodes.size)
       (sourceNodes zip destNodes).foreach { case (src, dst) =>
         val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
@@ -134,7 +134,8 @@ class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
   }
 
   println(s"Constellation: $nocName Finished parameter validation")
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     println(s"Constellation: $nocName Starting NoC RTL generation")
     val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
       val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))

src/main/scala/protocol/Tilelink.scala

@@ -337,7 +337,16 @@ case class TileLinkProtocolParams(
           nif_master.io.tilelink.a.valid := false.B
           nif_master.io.tilelink.c.valid := false.B
           nif_master.io.tilelink.e.valid := false.B
-          nif_master.io.tilelink <> protocol.in(i)
+
+          nif_master.io.tilelink.a <> protocol.in(i).a
+          protocol.in(i).d <> nif_master.io.tilelink.d
+
+          if (protocol.in(i).params.hasBCE) {
+            protocol.in(i).b <> nif_master.io.tilelink.b
+            nif_master.io.tilelink.c <> protocol.in(i).c
+            protocol.in(i).e <> nif_master.io.tilelink.e
+          }
+
           ingresses(i * 3 + 0).flit <> nif_master.io.flits.a
           ingresses(i * 3 + 1).flit <> nif_master.io.flits.c
           ingresses(i * 3 + 2).flit <> nif_master.io.flits.e
@@ -354,7 +363,16 @@ case class TileLinkProtocolParams(
           nif_slave.io.tilelink := DontCare
           nif_slave.io.tilelink.b.valid := false.B
           nif_slave.io.tilelink.d.valid := false.B
-          nif_slave.io.tilelink <> protocol.out(i)
+
+          protocol.out(i).a <> nif_slave.io.tilelink.a
+          nif_slave.io.tilelink.d <> protocol.out(i).d
+
+          if (protocol.out(i).params.hasBCE) {
+            nif_slave.io.tilelink.b <> protocol.out(i).b
+            protocol.out(i).c <> nif_slave.io.tilelink.c
+            nif_slave.io.tilelink.e <> protocol.out(i).e
+          }
+
           ingresses(i * 2 + 0 + edgesIn.size * 3).flit <> nif_slave.io.flits.b
           ingresses(i * 2 + 1 + edgesIn.size * 3).flit <> nif_slave.io.flits.d
           nif_slave.io.flits.a <> egresses(i * 3 + 0 + edgesIn.size * 2).flit

src/main/scala/router/EgressUnit.scala

@@ -12,9 +12,10 @@ import constellation.routing.{FlowRoutingBundle}
 class EgressUnit(coupleSAVA: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
   (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
 
-  val io = IO(new AbstractOutputUnitIO(inParams, ingressParams, cParam) {
+  class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
     val out = Decoupled(new EgressFlit(cParam.payloadBits))
-  })
+  }
+  val io = IO(new EgressUnitIO)
 
   val channel_empty = RegInit(true.B)
   val flow = Reg(new FlowRoutingBundle)

src/main/scala/router/IngressUnit.scala

@@ -18,9 +18,10 @@ class IngressUnit(
 )
   (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
 
-  val io = IO(new AbstractInputUnitIO(cParam, outParams, egressParams) {
+  class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
     val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
-  })
+  }
+  val io = IO(new IngressUnitIO)
 
   val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
   val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
@@ -119,8 +120,9 @@ class IngressUnit(
   out_bundle.valid := vcalloc_buffer.io.deq.fire()
   out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
   out_bundle.bits.flit.virt_channel_id := 0.U
-  val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_))
-  out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh, vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)))
+  val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
+  out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
+    vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
 
   io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
   io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready

src/main/scala/router/InputUnit.scala

@@ -164,9 +164,11 @@ class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
   val nVirtualChannels = cParam.nVirtualChannels
   val virtualChannelParams = cParam.virtualChannelParams
 
-  val io = IO(new AbstractInputUnitIO(cParam, outParams, egressParams) {
+  class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
     val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
-  })
+  }
+  val io = IO(new InputUnitIO)
+
   val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
 
   class InputState extends Bundle {
@@ -329,8 +331,8 @@ class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
     salloc_out.valid := salloc_arb.io.out(i).fire()
     salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
     val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
-    val channel_oh = vc_sel.map(_.reduce(_||_))
-    val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)))
+    val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
+    val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
     when (salloc_arb.io.out(i).fire()) {
       salloc_out.out_vid := virt_channel
       salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))

src/main/scala/router/OutputUnit.scala

@@ -52,9 +52,10 @@ abstract class AbstractOutputUnit(
 class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams)
   (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
 
-  val io = IO(new AbstractOutputUnitIO(inParams, ingressParams, cParam) {
+  class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
     val out = new Channel(cParam.asInstanceOf[ChannelParams])
-  })
+  }
+  val io = IO(new OutputUnitIO)
 
   class OutputState(val bufferSize: Int) extends Bundle {
     val occupied = Bool()

src/main/scala/router/vcalloc/MultiVCAllocator.scala

@@ -28,7 +28,7 @@ abstract class MultiVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) e
       Mux(io.channel_status(i)(j).available,
         outputAllocPolicy(
           oP.channelRoutingInfos(j),
-          io.req.map(_.bits.flow),
+          io.req.map(_.bits.flow).toSeq,
           in_allocs.map(_(i)(j)),
           io.out_allocs(i)(j).alloc
         ),
@@ -52,7 +52,7 @@ abstract class MultiVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters) e
   for (i <- 0 until allOutParams.size) {
     (0 until allOutParams(i).nVirtualChannels).map { j =>
       io.out_allocs(i)(j).alloc := in_allocs.map(_(i)(j)).orR && io.channel_status(i)(j).available
-      io.out_allocs(i)(j).flow := Mux1H(out_allocs(i)(j).asUInt, io.req.map(_.bits.flow))
+      io.out_allocs(i)(j).flow := Mux1H(out_allocs(i)(j).asUInt, io.req.map(_.bits.flow).toSeq)
     }
   }
 }

src/main/scala/router/vcalloc/Prioritizing.scala

@@ -48,14 +48,22 @@ trait Prioritizing { this: VCAllocator =>
         }}
       }}.flatten.flatten.flatten.flatten
 
-      val addr = (((inVId << (log2Ceil(allInParams.size))) | inId) << flow.getWidth) | flow.asUInt
+      class LookupBundle extends Bundle {
+        val vid = UInt((inVId.getWidth max 1).W)
+        val id = UInt((inId.getWidth max 1).W)
+        val flow = new FlowRoutingBundle
+      }
+
+      val addr_bundle = Wire(new LookupBundle)
+      val addr = addr_bundle.asUInt
+      addr_bundle.vid := inVId
+      addr_bundle.id := inId
+      addr_bundle.flow := flow
+
       val in_prio = (0 until allOutParams.size).map { i => (0 until allOutParams(i).nVirtualChannels).map { j =>
         val lookup = prio_map.filter(t => t.outId == i && t.outVId == j).map { e =>
-          val inVId = e.inVId << (log2Ceil(allInParams.size) + ingressIdBits + egressIdBits)
-          val inId = e.inId << (ingressIdBits + egressIdBits)
-          val ingress = e.flow.ingressId << egressIdBits
-          val egress = e.flow.egressId
-          (BitPat((inVId | inId | ingress | egress).U), BitPat((1 << e.prio).U))
+          val ref = (((e.inVId << addr_bundle.id.getWidth) | e.inId) << addr_bundle.flow.getWidth) | e.flow.asLiteral(flow)
+          (BitPat(ref.U), BitPat((1 << e.prio).U(nPrios.W)))
         }
         Mux(in(i)(j), DecodeLogic(addr, BitPat.dontCare(nPrios), lookup), 0.U(nPrios.W))
       }}

src/main/scala/router/vcalloc/SingleVCAllocator.scala

@@ -29,17 +29,17 @@ abstract class SingleVCAllocator(vP: VCAllocatorParams)(implicit p: Parameters)
       }
     }
 
-    in_arb_vals(i) := io.req(i).valid && in_arb_reqs(i).map(_.orR).orR
+    in_arb_vals(i) := io.req(i).valid && in_arb_reqs(i).map(_.orR).toSeq.orR
   }
 
   // Input arbitration
   io.req.foreach(_.ready := false.B)
   val in_alloc = Wire(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
-  val in_flow = Mux1H(in_arb_sel, io.req.map(_.bits.flow))
-  val in_vc = Mux1H(in_arb_sel, io.req.map(_.bits.in_vc))
+  val in_flow = Mux1H(in_arb_sel, io.req.map(_.bits.flow).toSeq)
+  val in_vc = Mux1H(in_arb_sel, io.req.map(_.bits.in_vc).toSeq)
   val in_vc_sel = Mux1H(in_arb_sel, in_arb_reqs)
   in_alloc := Mux(in_arb_vals.orR,
-    inputAllocPolicy(in_flow, in_vc_sel, OHToUInt(in_arb_sel), in_vc, io.req.map(_.fire).orR),
+    inputAllocPolicy(in_flow, in_vc_sel, OHToUInt(in_arb_sel), in_vc, io.req.map(_.fire).toSeq.orR),
     0.U.asTypeOf(in_alloc))
 
   // send allocation to inputunits

src/main/scala/routing/Types.scala

@@ -55,6 +55,17 @@ case class FlowRoutingInfo(
       f.ingress_node_id === ingressNodeId.U &&
       f.egress_node_id === egressNodeId.U)
   }
+  def asLiteral(b: FlowRoutingBundle): BigInt = {
+    Seq(
+      (vNetId        , b.vnet_id),
+      (ingressNode   , b.ingress_node),
+      (ingressNodeId , b.ingress_node_id),
+      (egressNode    , b.egress_node),
+      (egressNodeId  , b.egress_node_id)
+    ).foldLeft(0)((l, t) => {
+      (l << t._2.getWidth) | t._1
+    })
+  }
 }
 
 class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {

src/main/scala/test/AXI4TestHarness.scala

@@ -57,7 +57,8 @@ class AXI4NoCTester(implicit p: Parameters) extends LazyModule {
     := TLRAMModel(s"${name} Master $i")
     := m.node) }
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val finished = Output(Bool())
     })

src/main/scala/test/TLTestHarness.scala

@@ -49,7 +49,8 @@ class TLNoCTester(implicit p: Parameters) extends LazyModule {
     DisableMonitors { implicit p => ram.node := TLFragmenter(4, 256) } := TLDelayer(tParams.delay) := noc.node
   }
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
     val io = IO(new Bundle {
       val finished = Output(Bool())
     })