regress: port tests to not use partial connects

ucb-bar · Aug 21, 2023 · 3eb7fec · 3eb7fec
1 parent 272f959
commit 3eb7fec
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Showing 11 changed files with 270 additions and 1,503 deletions.
diff --git a/regress/FPU.fir b/regress/FPU.fir
diff --git a/regress/HwachaSequencer.fir b/regress/HwachaSequencer.fir
diff --git a/regress/ICache.fir b/regress/ICache.fir
@@ -419,12 +419,12 @@ circuit ICache :
     node _T_641 = eq(stall, UInt<1>("h00")) @[ICache.scala 149:46]
     reg _T_654 : UInt<1>[4], clock @[Reg.scala 34:16]
     when _T_641 : @[Reg.scala 35:19]
-      _T_654 <- s1_tag_hit @[Reg.scala 35:23]
+      _T_654 <= s1_tag_hit @[Reg.scala 35:23]
       skip @[Reg.scala 35:19]
     node _T_672 = eq(stall, UInt<1>("h00")) @[ICache.scala 150:40]
     reg _T_685 : UInt<64>[4], clock @[Reg.scala 34:16]
     when _T_672 : @[Reg.scala 35:19]
-      _T_685 <- s1_dout @[Reg.scala 35:23]
+      _T_685 <= s1_dout @[Reg.scala 35:23]
       skip @[Reg.scala 35:19]
     node _T_703 = mux(_T_654[0], _T_685[0], UInt<1>("h00")) @[Mux.scala 19:72]
     node _T_705 = mux(_T_654[1], _T_685[1], UInt<1>("h00")) @[Mux.scala 19:72]
@@ -536,7 +536,7 @@ circuit ICache :
     node _T_844 = cat(_T_843, _T_840) @[Cat.scala 30:58]
     _T_767.mask <= _T_844 @[Edges.scala 348:15]
     _T_767.data <= UInt<1>("h00") @[Edges.scala 349:15]
-    io.mem.0.a.bits <- _T_767 @[ICache.scala 155:17]
+    io.mem.0.a.bits <= _T_767 @[ICache.scala 155:17]
     io.mem.0.c.valid <= UInt<1>("h00") @[ICache.scala 159:18]
     io.mem.0.e.valid <= UInt<1>("h00") @[ICache.scala 160:18]
     node _T_848 = eq(UInt<2>("h00"), state) @[Conditional.scala 29:28]

diff --git a/regress/Rob.fir b/regress/Rob.fir
diff --git a/regress/RocketCore.fir b/regress/RocketCore.fir
diff --git a/src/main/scala/firrtl2/passes/ConvertFixedToSInt.scala b/src/main/scala/firrtl2/passes/ConvertFixedToSInt.scala
diff --git a/src/main/scala/firrtl2/passes/InferBinaryPoints.scala b/src/main/scala/firrtl2/passes/InferBinaryPoints.scala