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Gemmini tests with spike #25
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To change the systolic array dimension in Spike, you can change this line. Chipyard v1.3.0 should have worked... Do you know if any of the other tests also failed? Also, did you build Gemmini with your own configuration (like a different systolic array size) before running the Spike tests? I'll clone and run Chipyard 1.3.0 myself just to be sure, and I'll get back to you. |
Thanks for looking into it and the tip about the spike configuration. I didn't rebuild gemmini with a different configuration and the gemmini_params.h file has the default values. I compared the gemmini_params.h in the gemmini_rocc_tests and in riscv-isa-sim, they have the same parameters. All gemmini-rocc-test failed for me as baremetal test with spike except the mvin_scale and tiled_matmul_cpu. In the meantime i also tested the linux version of the tests with firemarshal - gemmini-tests.json - and spike. I attached the log, warning: big size: Btw. the verilator sim is working for the baremetal gemmini tests. |
Can you try running these commands?
And then try to run the |
Now it's working. Thank you! |
No problem. It turns out that the |
This update is necessary to match the gemmini_params.h in gemmini-rocc-tests used by chipyard 1.3.0. Solution: ucb-bar/gemmini#25 (comment)
I use chipyard 1.3.0 with gemmini caaf781 and ucb-bar/esp-isa-sim@13384ca. When running the gemmini baremetal tests, e.g.
spike --extension=gemmini build/bareMetalC/mvin_mvout_acc-baremetal
the tests fails. The Matrix output is null for all entries.
I also tried ucb-bar/esp-isa-sim@2e96965 with the same result.
RISCV toolchain is the esp-tools variant.
Can you give some hint for a working riscv-isa-sim and gemmini version combination?
The output for the mvin_mvout_acc-baremetal test is attached:
gemmini.log
A other question, is it possible to define a different array dimension for spike?
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