Fix arm post init

unicorn-engine · Dec 24, 2021 · cddc9cf · cddc9cf
1 parent 5b3a9e1
commit cddc9cf
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Showing 2 changed files with 54 additions and 0 deletions.
diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c
@@ -692,6 +692,19 @@ void arm_cpu_post_init(CPUState *obj)
         set_feature(&cpu->env, ARM_FEATURE_PMSA);
     }
 
+    if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
+        arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
+        cpu->reset_cbar = 0;
+    }
+
+    if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
+        cpu->reset_hivecs = false;
+    }
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+        cpu->rvbar = 0;
+    }
+
     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
         cpu->has_pmu = true;
     }
@@ -710,6 +723,21 @@ void arm_cpu_post_init(CPUState *obj)
     if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
         cpu->has_neon = true;
     }
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
+        arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
+        cpu->has_dsp = true;
+    }
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
+        cpu->has_mpu = true;
+    }
+
+    cpu->cfgend = false;
+
+    if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
+        cpu->gt_cntfrq_hz = NANOSECONDS_PER_SECOND / GTIMER_SCALE;
+    }
 }
 
 static void arm_cpu_finalize_features(ARMCPU *cpu)

diff --git a/tests/unit/test_arm.c b/tests/unit/test_arm.c
@@ -373,6 +373,31 @@ static void test_arm_v8()
     OK(uc_close(uc));
 }
 
+static void test_arm_thumb_smlabb()
+{
+    char code[] = "\x13\xfb\x01\x23";
+    uint32_t r_r1, r_r2, r_r3;
+    uc_engine *uc;
+
+    uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_THUMB, code, sizeof(code) - 1,
+                    UC_CPU_ARM_CORTEX_M7);
+
+    r_r3 = 5;
+    r_r1 = 7;
+    r_r2 = 9;
+    OK(uc_reg_write(uc, UC_ARM_REG_R3, &r_r3));
+    OK(uc_reg_write(uc, UC_ARM_REG_R1, &r_r1));
+    OK(uc_reg_write(uc, UC_ARM_REG_R2, &r_r2));
+
+    OK(uc_emu_start(uc, code_start | 1, code_start + sizeof(code) - 1, 0, 0));
+
+    OK(uc_reg_read(uc, UC_ARM_REG_R3, &r_r3));
+
+    TEST_CHECK(r_r3 == 5 * 7 + 9);
+
+    OK(uc_close(uc));
+}
+
 TEST_LIST = {{"test_arm_nop", test_arm_nop},
              {"test_arm_thumb_sub", test_arm_thumb_sub},
              {"test_armeb_sub", test_armeb_sub},
@@ -384,4 +409,5 @@ TEST_LIST = {{"test_arm_nop", test_arm_nop},
              {"test_arm_und32_to_svc32", test_arm_und32_to_svc32},
              {"test_arm_usr32_to_svc32", test_arm_usr32_to_svc32},
              {"test_arm_v8", test_arm_v8},
+             {"test_arm_thumb_smlabb", test_arm_thumb_smlabb},
              {NULL, NULL}};