Add CpuModel's for architectures to rust bindings

bindings/rust/src/arm.rs

@@ -171,3 +171,53 @@ impl From<RegisterARM> for i32 {
         r as i32
     }
 }
+
+#[repr(i32)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
+pub enum ArmCpuModel {
+    UC_CPU_ARM_926 = 0,
+    UC_CPU_ARM_946 = 1,
+    UC_CPU_ARM_1026 = 2,
+    UC_CPU_ARM_1136_R2 = 3,
+    UC_CPU_ARM_1136 = 4,
+    UC_CPU_ARM_1176 = 5,
+    UC_CPU_ARM_11MPCORE = 6,
+    UC_CPU_ARM_CORTEX_M0 = 7,
+    UC_CPU_ARM_CORTEX_M3 = 8,
+    UC_CPU_ARM_CORTEX_M4 = 9,
+    UC_CPU_ARM_CORTEX_M7 = 10,
+    UC_CPU_ARM_CORTEX_M33 = 11,
+    UC_CPU_ARM_CORTEX_R5 = 12,
+    UC_CPU_ARM_CORTEX_R5F = 13,
+    UC_CPU_ARM_CORTEX_A7 = 14,
+    UC_CPU_ARM_CORTEX_A8 = 15,
+    UC_CPU_ARM_CORTEX_A9 = 16,
+    UC_CPU_ARM_CORTEX_A15 = 17,
+    UC_CPU_ARM_TI925T = 18,
+    UC_CPU_ARM_SA1100 = 19,
+    UC_CPU_ARM_SA1110 = 20,
+    UC_CPU_ARM_PXA250 = 21,
+    UC_CPU_ARM_PXA255 = 22,
+    UC_CPU_ARM_PXA260 = 23,
+    UC_CPU_ARM_PXA261 = 24,
+    UC_CPU_ARM_PXA262 = 25,
+    UC_CPU_ARM_PXA270 = 26,
+    UC_CPU_ARM_PXA270A0 = 27,
+    UC_CPU_ARM_PXA270A1 = 28,
+    UC_CPU_ARM_PXA270B0 = 29,
+    UC_CPU_ARM_PXA270B1 = 30,
+    UC_CPU_ARM_PXA270C0 = 31,
+    UC_CPU_ARM_PXA270C5 = 32,
+}
+
+impl From<ArmCpuModel> for i32 {
+    fn from(value: ArmCpuModel) -> Self {
+        value as i32
+    }
+}
+
+impl From<&ArmCpuModel> for i32 {
+    fn from(value: &ArmCpuModel) -> Self {
+        *value as i32
+    }
+}

bindings/rust/src/arm64.rs

@@ -1,7 +1,8 @@
+#![allow(non_camel_case_types)]
+
 // ARM64 registers
 #[repr(C)]
 #[derive(PartialEq, Debug, Clone, Copy)]
-#[allow(non_camel_case_types)]
 pub enum RegisterARM64 {
     INVALID = 0,
     X29 = 1,
@@ -324,3 +325,24 @@ impl From<RegisterARM64> for i32 {
         r as i32
     }
 }
+
+#[repr(i32)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub enum Arm64CpuModel {
+    UC_CPU_ARM64_A57 = 0,
+    UC_CPU_ARM64_A53 = 1,
+    UC_CPU_ARM64_A72 = 2,
+    UC_CPU_ARM64_MAX = 3,
+}
+
+impl From<Arm64CpuModel> for i32 {
+    fn from(value: Arm64CpuModel) -> Self {
+        value as i32
+    }
+}
+
+impl From<&Arm64CpuModel> for i32 {
+    fn from(value: &Arm64CpuModel) -> Self {
+        (*value) as i32
+    }
+}

bindings/rust/src/lib.rs

@@ -34,10 +34,10 @@ extern crate std;
 
 #[macro_use]
 pub mod unicorn_const;
+pub mod ffi; // lets consumers call ffi if desired
 
 mod arm;
 mod arm64;
-mod ffi;
 mod m68k;
 mod mips;
 mod ppc;

bindings/rust/src/m68k.rs

@@ -1,3 +1,5 @@
+#![allow(non_camel_case_types)]
+
 // M68K registers
 #[repr(C)]
 #[derive(PartialEq, Debug, Clone, Copy)]
@@ -29,3 +31,29 @@ impl From<RegisterM68K> for i32 {
         r as i32
     }
 }
+
+#[repr(i32)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub enum M68kCpuModel {
+    UC_CPU_M68K_M5206 = 0,
+    UC_CPU_M68K_M68000 = 1,
+    UC_CPU_M68K_M68020 = 2,
+    UC_CPU_M68K_M68030 = 3,
+    UC_CPU_M68K_M68040 = 4,
+    UC_CPU_M68K_M68060 = 5,
+    UC_CPU_M68K_M5208 = 6,
+    UC_CPU_M68K_CFV4E = 7,
+    UC_CPU_M68K_ANY = 8,
+}
+
+impl From<M68kCpuModel> for i32 {
+    fn from(value: M68kCpuModel) -> Self {
+        value as i32
+    }
+}
+
+impl From<&M68kCpuModel> for i32 {
+    fn from(value: &M68kCpuModel) -> Self {
+        (*value) as i32
+    }
+}

bindings/rust/src/mips.rs

@@ -251,3 +251,36 @@ impl From<RegisterMIPS> for i32 {
         r as i32
     }
 }
+
+#[repr(i32)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+pub enum Mips32CpuModel {
+    UC_CPU_MIPS32_4KC = 0,
+    UC_CPU_MIPS32_4KM = 1,
+    UC_CPU_MIPS32_4KECR1 = 2,
+    UC_CPU_MIPS32_4KEMR1 = 3,
+    UC_CPU_MIPS32_4KEC = 4,
+    UC_CPU_MIPS32_4KEM = 5,
+    UC_CPU_MIPS32_24KC = 6,
+    UC_CPU_MIPS32_24KEC = 7,
+    UC_CPU_MIPS32_24KF = 8,
+    UC_CPU_MIPS32_34KF = 9,
+    UC_CPU_MIPS32_74KF = 10,
+    UC_CPU_MIPS32_M14K = 11,
+    UC_CPU_MIPS32_M14KC = 12,
+    UC_CPU_MIPS32_P5600 = 13,
+    UC_CPU_MIPS32_MIPS32R6_GENERIC = 14,
+    UC_CPU_MIPS32_I7200 = 15,
+}
+
+impl From<Mips32CpuModel> for i32 {
+    fn from(value: Mips32CpuModel) -> Self {
+        value as i32
+    }
+}
+
+impl From<&Mips32CpuModel> for i32 {
+    fn from(value: &Mips32CpuModel) -> Self {
+        *value as i32
+    }
+}