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88 Open 175 Closed
88 Open 175 Closed
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Issues list

Can't shift a 48 bit number using DSP internal shifters, but can shift 47 bit number?
#472 opened Sep 23, 2024 by gussmith23
yosys-plugin segfaults on multi-module designs
#466 opened Sep 6, 2024 by cknizek
5
Support 17-bit-shifted PCIN input on DSP48E2
#464 opened Sep 4, 2024 by gussmith23
1
1
Map to Skywater 130 DesignWare libraries research
#462 opened Aug 26, 2024 by gussmith23
1
Including bsg_dff_chain.sv into a Lakeroad integration test causes test failure
#458 opened Aug 19, 2024 by cknizek
3
Prototype memory mapping with Lakeroad
#457 opened Aug 9, 2024 by gussmith23
Better error messages when solvers aren't found
#456 opened Jul 29, 2024 by gussmith23
Enable rosette's output-smt via a command-line option good first issue Good for newcomers
#453 opened Jul 9, 2024 by gussmith23
Can we cut down testing time enough to just run on GitHub runners?
#450 opened Jul 5, 2024 by gussmith23
Node glibc Github Actions issue
#449 opened Jul 5, 2024 by gussmith23
2
Debugging Virtex DSP48E1 bug
#445 opened Jun 26, 2024 by gussmith23
4 of 5 tasks
7
Spaces in paths break portfolio solver
#436 opened Apr 30, 2024 by gussmith23
Run examples during release CI, to make sure they work
#434 opened Apr 30, 2024 by gussmith23
Lakeroad portfolio help should defer to Lakeroad Rosette help
#433 opened Apr 29, 2024 by gussmith23
Fix inefficient Docker caching in CI
#426 opened Feb 25, 2024 by gussmith23
1
--help flag on main.rkt isn't printing entire help strings for each flag
#423 opened Feb 24, 2024 by gussmith23
Make sure that private files are in lakeroad-private, public files are in lakeroad, and document the difference
#415 opened Jan 25, 2024 by gussmith23
Documentation overhaul cleanup Code cleanup/refactoring
#414 opened Jan 25, 2024 by gussmith23
Make flags consistent across various scripts in bin/ cleanup Code cleanup/refactoring
#413 opened Jan 25, 2024 by gussmith23
Make sure correct Racket (8.9) is installed in CI
#412 opened Jan 24, 2024 by gussmith23
Add integration tests that synthesize and simulate w/ sketches other than the dsp sketch
#410 opened Dec 17, 2023 by gussmith23
Add tests that use Yices2
#407 opened Dec 14, 2023 by gussmith23
Given an eclass that may contain loops, extract a representative egglog Pertaining to lakeroad-egglog (aka Churchroad)
#405 opened Dec 9, 2023 by gussmith23
2 tasks
Enumerate all submodules in the permuter, modulo rewrites egglog Pertaining to lakeroad-egglog (aka Churchroad)
#403 opened Dec 3, 2023 by gussmith23
3 tasks
4
Project idea: more efficient mappings of ASIC standard library cells to FPGAs for emulation research
#401 opened Nov 29, 2023 by gussmith23
1
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