HY523 RISC-V

RV32IC with support for stream transactions

input the pipeline register produced by IF stage (IF_STATE) output the pipeline register ID_STATE

Name		Name	Last commit message	Last commit date
Latest commit History 134 Commits
IF_ID_test		IF_ID_test
data_files		data_files
dmem_state		dmem_state
docs		docs
ex_state		ex_state
hex_files		hex_files
report		report
risc-v_32ic		risc-v_32ic
synthesis		synthesis
BIS.pvk		BIS.pvk
ISA.sv		ISA.sv
Makefile		Makefile
PipelineReg.pvk		PipelineReg.pvk
PipelineRegs.sv		PipelineRegs.sv
README.md		README.md
addi.comments		addi.comments
branch_code.bin		branch_code.bin
codemem_compressed0.hex		codemem_compressed0.hex
command.log		command.log
comp_instr_decoder.sv		comp_instr_decoder.sv
comp_instr_demux.sv		comp_instr_demux.sv
comp_instr_fsm.sv		comp_instr_fsm.sv
comp_instr_top.sv		comp_instr_top.sv
compressed_instr.bin		compressed_instr.bin
crte_000001657.txt		crte_000001657.txt
datamem.hex		datamem.hex
datamemem_compressed0.hex		datamemem_compressed0.hex
default.svf		default.svf
dmem_tb.sv		dmem_tb.sv
fibonacci.c		fibonacci.c
fibonacci_code.hex		fibonacci_code.hex
fibonacci_data.hex		fibonacci_data.hex
filenames.log		filenames.log
instructions.sv		instructions.sv
itype_code.hex		itype_code.hex
itype_data.hex		itype_data.hex
ldst_code.hex		ldst_code.hex
mem.hex		mem.hex
regfile.data		regfile.data
slides.pdf		slides.pdf
sram.sv		sram.sv
testbench.sv		testbench.sv
top.sv		top.sv
top_test.sv		top_test.sv