Get the sign/logic right

varnishcache · Jan 16, 2018 · fd06bc0 · fd06bc0
1 parent 5332d21
commit fd06bc0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/bin/varnishtest/vtc_process.c b/bin/varnishtest/vtc_process.c
@@ -324,7 +324,7 @@ process_thread(void *priv)
 	if (p->expect_signal >= 0 && sig != p->expect_signal)
 		vtc_fatal(p->vl, "Expected signal %d got %d",
 			p->expect_signal, sig);
-	else if (sig && sig != p->expect_signal)
+	else if (sig != 0 && sig != -p->expect_signal)
 		vtc_fatal(p->vl, "Expected signal %d got %d",
 			-p->expect_signal, sig);
 	if (ext != p->expect_exit)