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Tests: Add a test for misc optimizations in V3Const.cpp
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#!/usr/bin/env perl | ||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } | ||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition | ||
# | ||
# Copyright 2003 by Wilson Snyder. This program is free software; you | ||
# can redistribute it and/or modify it under the terms of either the GNU | ||
# Lesser General Public License Version 3 or the Perl Artistic License | ||
# Version 2.0. | ||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 | ||
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scenarios(simulator => 1); | ||
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compile( | ||
verilator_flags2=>["-Wno-UNOPTTHREADS", "--stats"], | ||
); | ||
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execute( | ||
check_finished => 1, | ||
); | ||
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if ($Self->{vlt}) { | ||
file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 2); | ||
} | ||
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ok(1); | ||
1; |
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// DESCRIPTION: Verilator: Verilog Test module | ||
// | ||
// This file ONLY is placed under the Creative Commons Public Domain, for | ||
// any use, without warranty, 2021 Yutetsu TAKATSUKASA. | ||
// SPDX-License-Identifier: CC0-1.0 | ||
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import "DPI-C" context function int import_func0(); | ||
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module t(/*AUTOARG*/ | ||
// Inputs | ||
clk | ||
); | ||
input clk; | ||
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integer cyc=0; | ||
reg [63:0] crc; | ||
reg [63:0] sum; | ||
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// Take CRC data and apply to testblock inputs | ||
wire [31:0] in = crc[31:0]; | ||
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wire [31:0] i = crc[31:0]; | ||
wire out; | ||
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Test test( | ||
// Outputs | ||
.out (out), | ||
// Inputs | ||
.clk (clk), | ||
.i (i[31:0])); | ||
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wire [63:0] result = {63'b0, out}; | ||
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// Test loop | ||
always @ (posedge clk) begin | ||
`ifdef TEST_VERBOSE | ||
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); | ||
`endif | ||
cyc <= cyc + 1; | ||
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; | ||
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; | ||
if (cyc == 0) begin | ||
// Setup | ||
crc <= 64'h5aef0c8d_d70a4497; | ||
sum <= '0; | ||
end | ||
else if (cyc < 10) begin | ||
sum <= '0; | ||
end | ||
else if (cyc == 99) begin | ||
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); | ||
if (crc !== 64'hc77bb9b3784ea091) $stop; | ||
if (import_func0() < 95) $stop; // expected to return around 100 | ||
// What checksum will we end up with (above print should match) | ||
`define EXPECTED_SUM 64'hbb2d9709592f64bd | ||
if (sum !== `EXPECTED_SUM) $stop; | ||
$write("*-* All Finished *-*\n"); | ||
$finish; | ||
end | ||
end | ||
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endmodule | ||
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module Test(/*AUTOARG*/ | ||
// Outputs | ||
out, | ||
// Inputs | ||
clk, i | ||
); | ||
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input clk; | ||
input [31:0] i; | ||
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output wire out; | ||
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logic [1:0] tmp; | ||
assign out = ^tmp; | ||
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always_ff @(posedge clk) begin | ||
tmp[0] <= i[0]; | ||
tmp[1] <= ^(0 * import_func0()); // import_func0 has side effect, so must be executed anyway. | ||
end | ||
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`systemc_implementation | ||
extern "C" int import_func0() { | ||
static int c = 0; | ||
return ++c; | ||
} | ||
`verilog | ||
endmodule |