FST regression tests fail instead of skip if fst2vcd isn't installed

[veripoolbot]

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Author Name: Todd Strader (@toddstrader)
Original Redmine Issue: 1417 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)

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$ t/t_trace_array_fst.pl 
======================================================================
dist/t_trace_array_fst: ==================================================
-Skip: dist/t_trace_array_fst: scenario 'dist' not enabled for test
dist/t_trace_array_fst: %Skip: Skip: scenario 'dist' not enabled for test
==SUMMARY: Left 1  Passed 0  Unsup 0  Skipped 0  Failed 0
======================================================================
vlt/t_trace_array_fst: ==================================================
vlt/t_trace_array_fst: Compile
         perl ../bin/verilator --prefix Vt_trace_array_fst --x-assign unique -cc -Mdir obj_vlt/t_trace_array_fst -OD --debug-check --comp-limit-members 10 --cc --trace-fst --trace-structs --clk clk  -f input.vc +define+TEST_OBJ_DIR=obj_vlt/t_trace_array_fst t/t_trace_array.v    > obj_vlt/t_trace_array_fst/vlt_compile.log
vlt/t_trace_array_fst: GCC
         make -C obj_vlt/t_trace_array_fst -f /usr/scratch/devs/verilator/test_regress/Makefile_obj VM_PREFIX=Vt_trace_array_fst TEST_OBJ_DIR=obj_vlt/t_trace_array_fst CPPFLAGS_DRIVER=-DT_TRACE_ARRAY_FST    Vt_trace_array_fst    > obj_vlt/t_trace_array_fst/vlt_gcc.log
make: Entering directory '/usr/scratch/devs/verilator/test_regress/obj_vlt/t_trace_array_fst'
/usr/local/bin/perl /usr/scratch/devs/verilator/test_regress/../bin/verilator_includer -DVL_INLINE_OPT=inline Vt_trace_array_fst__main.cpp /usr/scratch/devs/verilator/test_regress/../include/verilated.cpp /usr/scratch/devs/verilator/test_regress/../include/verilated_fst_c.cpp Vt_trace_array_fst.cpp Vt_trace_array_fst__Trace.cpp Vt_trace_array_fst__Syms.cpp Vt_trace_array_fst__Trace__Slow.cpp > Vt_trace_array_fst__ALLboth.cpp
g++  -I.  -MMD -I/usr/scratch/devs/verilator/test_regress/../include -I/usr/scratch/devs/verilator/test_regress/../include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow      -DVERILATOR=1 -DVL_DEBUG=1 -DTEST_OBJ_DIR=obj_vlt/t_trace_array_fst -DVM_PREFIX=Vt_trace_array_fst -DVM_PREFIX_INCLUDE="<Vt_trace_array_fst.h>" -DT_TRACE_ARRAY_FST    -c -o Vt_trace_array_fst__ALLboth.o Vt_trace_array_fst__ALLboth.cpp
g++    -g Vt_trace_array_fst__ALLboth.o   -lz  -o Vt_trace_array_fst -lm -lstdc++ 2>&1
make: Leaving directory '/usr/scratch/devs/verilator/test_regress/obj_vlt/t_trace_array_fst'
vlt/t_trace_array_fst: Run
         obj_vlt/t_trace_array_fst/Vt_trace_array_fst    > obj_vlt/t_trace_array_fst/vlt_sim.log
*-* All Finished *-*
- t/t_trace_array.v:23: Verilog $finish
Can't exec "fst2vcd": No such file or directory at ./driver.pl line 1680.
-Skip: vlt/t_trace_array_fst: No fst2vcd installed

%Warning: vlt/t_trace_array_fst: Vcd_identical file does not exist obj_vlt/t_trace_array_fst/simx-fst2vcd.vcd

vlt/t_trace_array_fst: %Error: Vcd_identical file does not exist obj_vlt/t_trace_array_fst/simx-fst2vcd.vcd
vlt/t_trace_array_fst: FAILED: ************************************************************
==SUMMARY: Left 0  Passed 0  Unsup 0  Skipped 0  Failed 1

======================================================================
TESTS Passed 0  Unsup 0  Skipped 0  Failed 1  Time 0:01
         #vlt/t_trace_array_fst: %Error: Vcd_identical file does not exist obj_vlt/t_trace_array_fst/simx-fst2vcd.vcd
                 make && test_regress/t/t_trace_array_fst.pl  --vlt
TESTS Passed 0  Unsup 0  Skipped 0  Failed 1  Time 0:01

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-04-11T00:52:11Z

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Fixed in git towards 4.014.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-05-09T01:38:00Z

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In 4.014.