Width mismatch warnings #350
Labels
area: configure/compiling
Issue involves configuring or compilating Verilator itself
resolution: wontfix
Closed; work won't continue on an issue or pull request
Author Name: Amin Firoozshahian
Original Redmine Issue: 350 from https://www.veripool.org
It seems that when assigning constant expressions to a signal, Verilator expects the LSH to be as wide as the widest parameter on the RHS, rather than the result of the expression. For example, when compiling the following code:
gets the following warning:
%Warning-WIDTH: test.v:15: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 6 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
%Error: Command Failed verilator_bin --cc test.v --top-module test
This is while `NUM-1 fits exactly in the 5 bits provided by the LHS signal.
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