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-- RUN ---------------------
obj_dir/Vtop +trace
SystemC 2.3.4_pub_rev_20190614-Accellera --- Feb 18 2023 18:31:47
Copyright (c) 1996-2019 by all Contributors,
ALL RIGHTS RESERVED
[0] Model running...
Enabling waves into logs/vlt_dump.vcd...
-V{t1,1} 'act' region trigger index 0 is active: @(posedge __Vcellinp__top__fastclk)
%Error: top.v:11: Active region did not converge.
Aborting...
gmake[2]: *** [Makefile:81: run] Abort trap
gmake[2]: Leaving directory '/usr/ports/cad/verilator/work/verilator-5.010/examples/make_tracing_sc'
gmake[1]: *** [Makefile:177: examples] Error 10
gmake[1]: Leaving directory '/usr/ports/cad/verilator/work/verilator-5.010'
*** Error code 1
Version: 5.010
clang-14
FreeBSD 13.2
The text was updated successfully, but these errors were encountered:
Given this passes on Ubuntu, it will likely require you debug it. Also you could try a git bisect, but I wouldn't be surprised if it is some change that is not the direct problem. Also maybe try using the address sanitizer at runtime ("-CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined")
Tests fail:
Version: 5.010
clang-14
FreeBSD 13.2
The text was updated successfully, but these errors were encountered: