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Support generating SAIF file for power estimation #5037

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ayanbanrj opened this issue Apr 5, 2024 · 2 comments
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Support generating SAIF file for power estimation #5037

ayanbanrj opened this issue Apr 5, 2024 · 2 comments
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resolution: abandoned Closed; not enough information or otherwise never finished

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@ayanbanrj
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Switching Activity Interchange Format (SAIF) files are used by physical implementation tools to perform power estimation and optimization, based on signal switching activity extracted from simulations. It would be great if Verilator could natively generate simulation traces in SAIF format because many tools (for example, Vivado) don't support VCD files as input for power estimation.

The SAIF format is described in IEEE Std 1801-2018, Annex I. Most commercial simulators support SAIF file generation.

May we assist you in trying to fix this in Verilator yourself?

Yes, I can attempt.

@ayanbanrj ayanbanrj added the new New issue not seen by maintainers label Apr 5, 2024
@wsnyder
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wsnyder commented Apr 5, 2024

Most power vendors flows have a converter, for example Synopsys' vcd2saif. Do you have that?

While Verilator could do this, is it a better ore general solution to e.g. extend gtkwave to convert formats? Then all simulators have a open source converter.

@wsnyder wsnyder added status: discussion Issue is waiting for discussions to resolve and removed new New issue not seen by maintainers labels Apr 12, 2024
@wsnyder wsnyder added resolution: abandoned Closed; not enough information or otherwise never finished and removed status: discussion Issue is waiting for discussions to resolve labels Apr 28, 2024
@wsnyder
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wsnyder commented Apr 28, 2024

Didn't hear back - presuming gtkwave improvement is an option.

@wsnyder wsnyder closed this as not planned Won't fix, can't repro, duplicate, stale Apr 28, 2024
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Labels
resolution: abandoned Closed; not enough information or otherwise never finished
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