Error-BLKANDNBLK with nested modules in generate block

[veripoolbot]

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Author Name: Krzysztof Jankowski
Original Redmine Issue: 648 from https://www.veripool.org

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The attached code gives error: ??%Error-BLKANDNBLK: condgen.sv:29: Unsupported: Blocked and non-blocking assignments to same variable: v.datat??.
When code gets pasted directly in place of module then the entire example compiles just fine.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2013-05-22T02:41:22Z

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I'm not immediately sure how to fix this. The conflict is at that port since a single bit is selected that is effectively the same as an assignment, causing the message.

The good news is for now you can lint_off that error (it's an error because it can cause bad results if otherwise ignored)

// verilator lint_off BLKANDNBLK
logic [7:0] 	      datat;
// verilator lint_on BLKANDNBLK

Test added as t_param_if_blk.

[veripoolbot]

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Original Redmine Comment
Author Name: Olivier D'Arcy
Original Date: 2019-01-26T04:28:27Z

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Hi, I experience the same kind of issue with conditional generate statements.

Here (codegen2.sv attached) is another code example that highlights the problem.
You need to remove the lint pragmas. You will hit the Error BLKANDNBLK. Then if you add the lint pragmas for BLKANDNBLK, you get a MULTIDRIVEN warning which prevents the code from compiling. Adding the lint pragmas for the MULTIDRIVEN warning solves the problem.

I was able to go around it by using lint off pragmas.

Still my RISCV RTL codebase heavily uses the generate if/else constructs so I get tons of such BLKANDNBLK errors. Some RTL sources are from third party (memory models generated by memory compilers, etc) so inserting pragmas in these files is not an ideal solution.