Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to…

…-routing

.gitignore

@@ -45,6 +45,11 @@ ODIN_II/SRC/verilog_flex.c
 *.o
 *.a
 
+#
+#Python
+#
+*.pyc
+
 #
 #Vim
 #

Makefile

@@ -2,7 +2,7 @@
 # Makefile to build CAD tools in Verilog-to-Routing (VTR) Framework #
 #####################################################################
 
-SUBDIRS = ODIN_II vpr abc_with_bb_support libarchfpga liblog ace2 libsdc_parse
+SUBDIRS = abc_with_bb_support ODIN_II vpr libarchfpga liblog ace2 libsdc_parse
 
 all: notifications subdirs
 

ODIN_II/Makefile

@@ -12,11 +12,15 @@ EXEO = odin_II.exe
 
 DEBUG_FLAGS = -g -DYYERROR_VERBOSE
 
+ABC_DIR = ../abc_with_bb_support
+ABC_AR  = $(ABC_DIR)/libabc.a
+ABC_INC = -I $(ABC_DIR)/src/bdd/cudd -I $(ABC_DIR)/src/bdd/epd -I $(ABC_DIR)/src/bdd/mtr -I $(ABC_DIR)/src/misc/st
+
 #OPT_FLAGS = -O2 
 # Use this value of OPT_FLAGS to simulate in parallel (requires GCC >= 4.2)
 #OPT_FLAGS = -O2 -fopenmp 
 
-INC_FLAGS =  -I../libarchfpga/include -I../libcommon_c++/SRC/TIO_InputOutputHandlers
+INC_FLAGS =  -I../libarchfpga/include -I../libcommon_c++/SRC/TIO_InputOutputHandlers $(ABC_INC)
 LIB = -L../libarchfpga -larchfpga -lm -ldl
 C_DIRECTIVE = -DVPR6 -DUSING_BISON
 
@@ -84,7 +88,7 @@ DEP = $(OBJ:.o=.d)
 all: CTAGS $(EXEO)
 
 $(EXEO): $(OBJ)
-	$(CC) $(C_FLAGS) $(FLAGS) $(OBJ) -o $(EXEO) $(LIB)
+	$(CC) $(C_FLAGS) $(FLAGS) $(OBJ) -o $(EXEO) $(LIB) $(ABC_AR)
 
 CTAGS :
 	@ cd SRC && ctags *.[ch]