fixed

.github/labeler.yml

@@ -21,6 +21,11 @@ Odin:
  - odin_ii/**/*
  - odin2_helper/*
  - odin2_helper/**/*
+Parmys:
+ - parmys/*
+ - parmys/**/*
+ - yosys/*
+ - yosys/**/*
 VPR:
  - vpr/*
  - vpr/**/*

vtr_flow/parse/parse_config/adders.txt

@@ -1,6 +1,6 @@
 %include "common/vtr_flow.txt"
 %include "common/odin.txt"
-%include "common/yosys.txt"
+%include "common/parmys.txt"
 %include "common/abc.txt"
 %include "common/ace.txt"
 

vtr_flow/parse/parse_config/common/parmys.txt

@@ -0,0 +1,4 @@
+#Parmys Run-time Metrics
+parmys_synth_time;parmys.out;\s*User time \(seconds\): (.*)
+max_parmys_mem;parmys.out;\s*Maximum resident set size \(kbytes\): (\d+)
+

vtr_flow/parse/parse_config/vpr_fixed_chan_width.txt

@@ -3,7 +3,7 @@
 
 %include "common/vtr_flow.txt"
 %include "common/odin.txt"
-%include "common/yosys.txt"
+%include "common/parmys.txt"
 %include "common/abc.txt"
 %include "common/ace.txt"
 

vtr_flow/parse/parse_config/vpr_no_timing.txt

@@ -1,6 +1,6 @@
 %include "common/vtr_flow.txt"
 %include "common/odin.txt"
-%include "common/yosys.txt"
+%include "common/parmys.txt"
 %include "common/abc.txt"
 %include "common/ace.txt"
 

vtr_flow/parse/parse_config/vpr_standard.txt

@@ -3,7 +3,7 @@
 
 %include "common/vtr_flow.txt"
 %include "common/odin.txt"
-%include "common/yosys.txt"
+%include "common/parmys.txt"
 %include "common/abc.txt"
 %include "common/ace.txt"
 

vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/config.txt

@@ -0,0 +1,36 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/freecores
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=aes_cipher.v
+circuit_list_add=aes_inv_cipher.v
+circuit_list_add=8051.v
+circuit_list_add=ethmac.v
+#circuit_list_add=dma_axi32.v
+#circuit_list_add=dma_axi64.v
+#circuit_list_add=i2c.v
+circuit_list_add=mips_16.v
+circuit_list_add=xtea.v
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+#Script parameters
+script_params=-track_memory_usage -end parmys

vtr_flow/tasks/regression_tests/parmys_reg_basic/freecores/config/golden_results.txt

@@ -0,0 +1,7 @@
+ arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
+ k6_frac_N10_frac_chain_mem32K_40nm.xml	  aes_cipher.v	  common	  18.53	  parmys	  449.26 MiB	  	  -1	  -1	  15.62	  460044	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  success	  unknown	  unknown	  unknown	  unknown	  dev	  /home/dani/CLionProjects/vtr-verilog-to-routing	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6_frac_N10_frac_chain_mem32K_40nm.xml	  aes_inv_cipher.v	  common	  18.57	  parmys	  456.23 MiB	  	  -1	  -1	  16.18	  467176	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  success	  unknown	  unknown	  unknown	  unknown	  dev	  /home/dani/CLionProjects/vtr-verilog-to-routing	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6_frac_N10_frac_chain_mem32K_40nm.xml	  8051.v	  common	  9.39	  parmys	  72.02 MiB	  	  -1	  -1	  7.45	  73744	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  success	  unknown	  unknown	  unknown	  unknown	  dev	  /home/dani/CLionProjects/vtr-verilog-to-routing	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6_frac_N10_frac_chain_mem32K_40nm.xml	  ethmac.v	  common	  10.80	  parmys	  105.79 MiB	  	  -1	  -1	  8.57	  108328	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  success	  unknown	  unknown	  unknown	  unknown	  dev	  /home/dani/CLionProjects/vtr-verilog-to-routing	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6_frac_N10_frac_chain_mem32K_40nm.xml	  mips_16.v	  common	  2.22	  parmys	  23.50 MiB	  	  -1	  -1	  0.48	  24064	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  success	  unknown	  unknown	  unknown	  unknown	  dev	  /home/dani/CLionProjects/vtr-verilog-to-routing	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 
+ k6_frac_N10_frac_chain_mem32K_40nm.xml	  xtea.v	  common	  2.60	  parmys	  32.87 MiB	  	  -1	  -1	  0.78	  33660	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  success	  unknown	  unknown	  unknown	  unknown	  dev	  /home/dani/CLionProjects/vtr-verilog-to-routing	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	  -1	 

vtr_flow/tasks/regression_tests/parmys_reg_basic/koios/config/config.txt

@@ -0,0 +1,49 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/verilog/koios
+
+# Path to directory of architectures to use
+archs_dir=arch/COFFE_22nm
+
+# Directory containing the verilog includes file(s)
+includes_dir=benchmarks/verilog/koios
+
+# Add circuits to list to sweep
+circuit_list_add=tpu_like.small.os.v
+circuit_list_add=tpu_like.small.ws.v
+circuit_list_add=dla_like.small.v
+circuit_list_add=bnn.v
+circuit_list_add=attention_layer.v
+circuit_list_add=conv_layer_hls.v
+circuit_list_add=conv_layer.v
+circuit_list_add=eltwise_layer.v
+circuit_list_add=robot_rl.v
+circuit_list_add=reduction_layer.v
+circuit_list_add=spmv.v
+circuit_list_add=softmax.v
+
+# Add architectures to list to sweep
+arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml
+
+# Add include files to the list.
+# Some benchmarks instantiate hard dsp and memory blocks 
+# This functionality is guarded under the `complex_dsp` and `hard_mem` macros. 
+# The hard_block_include.v file 
+# defines this macros, thereby enabling instantiations of the hard blocks
+include_list_add=hard_block_include.v
+
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+#Script parameters
+script_params=-track_memory_usage -end parmys