Update documentation references.

doc/arch/tutorial/xilinx_virtex_6_like.rst

@@ -10,7 +10,7 @@ In this example, we describe the Xilinx Virtex-6 FPGA logic slice, shown in :num
 
 .. figure:: v6_logic_slice.*
 
-    Commercial FPGA logic block slice (taken from Virtex-6 description [1])
+    Commercial FPGA logic block slice (Virtex-6 :cite:`xilinx_virtex_6_clb`)
 
 .. code-block:: xml
 

doc/requirements.txt

@@ -1,4 +1,6 @@
 #Python requirements file for building documentation
-#
-#
+# used by Read The Docs to install python required 
+# modules with pip.
+
+#Handle references in bibtex format
 sphinxcontrib-bibtex

doc/z_references.bib

@@ -7,7 +7,7 @@ @book{betz_arch_cad
     month = {mar},
     publisher = {Kluwer Academic Publishers},
     title = {Architecture and CAD for Deep-Submicron FPGAs},
-    year = {1999}
+    year = {1999},
 }
 
 @inproceedings{betz_vpr,
@@ -19,7 +19,7 @@ @inproceedings{betz_vpr
     isbn = {3-540-63465-7},
     pages = {213--222},
     numpages = {10},
-    url = {http://dl.acm.org/citation.cfm?id=647924.738755},
+    doi = {10.1007/3-540-63465-7_226},
     acmid = {738755},
     publisher = {Springer-Verlag},
     address = {London, UK},
@@ -42,7 +42,6 @@ @inproceedings{marquardt_timing_driven_placement
     location = {Monterey, California, USA},
     pages = {203--213},
     numpages = {11},
-    url = {http://doi.acm.org/10.1145/329166.329208},
     doi = {10.1145/329166.329208},
     acmid = {329208},
     publisher = {ACM},
@@ -52,9 +51,10 @@ @inproceedings{marquardt_timing_driven_placement
 @inproceedings{betz_cluster_based_logic_blocks,
     author = {Betz, V. and Rose, J.},
     title = {Cluster-Based Logic Blocks for FPGAs:  Area-Efficiency vs. Input Sharing and Size},
-    booktitle = {CICC},
+    booktitle={Custom Integrated Circuits Conference},
     pages = {551--554},
     year = {1997},
+    doi={10.1109/CICC.1997.606687},
 }
 
 @inproceedings{marquardt_timing_driven_packing,
@@ -63,6 +63,7 @@ @inproceedings{marquardt_timing_driven_packing
     booktitle = {FPGA},
     pages = {37--46},
     year = {1999},
+    doi = {10.1145/296399.296426},
 }
 
 @inproceedings{betz_directional_bias_routing_arch,
@@ -75,7 +76,7 @@ @inproceedings{betz_directional_bias_routing_arch
     location = {San Jose, California, USA},
     pages = {652--659},
     numpages = {8},
-    url = {http://dl.acm.org/citation.cfm?id=244522.244948},
+    doi = {10.1109/ICCAD.1996.571342},
     acmid = {244948},
     publisher = {IEEE Computer Society},
     address = {Washington, DC, USA},
@@ -93,18 +94,27 @@ @techreport{betz_biased_global_routing_tech_report
 }
 
 @inproceedings{betz_automatic_generation_of_fpga_routing,
-    author = {Betz, V. and Rose, J.},
-    title = {Automatic Generation of FPGA Routing Architectures from High-Level Descriptions},
-    booktitle = {ACM/SIGDA Int. Symp. on FPGAs},
-    pages = {175--184},
+    author = {Betz, Vaughn and Rose, Jonathan},
+    title = {Automatic Generation of FPGA Routing Architectures from High-level Descriptions},
+    booktitle = {Int. Symp. on Field Programmable Gate Arrays},
+    series = {FPGA},
     year = {2000},
+    isbn = {1-58113-193-3},
+    location = {Monterey, California, USA},
+    pages = {175--184},
+    numpages = {10},
+    doi = {10.1145/329166.329203},
+    acmid = {329203},
+    publisher = {ACM},
+    address = {New York, NY, USA},
 }
 
 @book{brown_fpgas,
     author = {Brown, S. and Francis, R. and Rose, J. and Vranesic, Z.},
     title = {Field-Programmable Gate Arrays},
     publisher = {Kluwer Academic Publishers},
     year = {1992},
+    isbn = {978-0-7923-9248-4},
 }
 
 @phdthesis{wilton_phd,
@@ -116,12 +126,21 @@ @phdthesis{wilton_phd
 }
 
 @article{chang_universal_switch_modules,
-    author = {Chang, Y. W. and Wong, D. F. and Wong, C. K.},
+    author = {Chang, Yao-Wen and Wong, D. F. and Wong, C. K.},
     title = {Universal Switch Modules for FPGA Design},
-    journal = {ACM Trans. on Design Automation of Electronic Systems},
-    month = {jan},
+    journal = {ACM Trans. Des. Autom. Electron. Syst.},
+    issue_date = {Jan. 1996},
+    volume = {1},
+    number = {1},
+    month = jan,
     year = {1996},
-    pages = {80-101},
+    issn = {1084-4309},
+    pages = {80--101},
+    numpages = {22},
+    doi = {10.1145/225871.225886},
+    acmid = {225886},
+    publisher = {ACM},
+    address = {New York, NY, USA},
 }
 
 @inproceedings{lemieux_directional_and_singale_driver_wires,
@@ -130,6 +149,7 @@ @inproceedings{lemieux_directional_and_singale_driver_wires
     booktitle = {International Conference on Field-Programmable Technology},
     pages = {41--48},
     year = {2004},
+    doi = {10.1109/FPT.2004.1393249},
 }
 
 
@@ -139,7 +159,7 @@ @inproceedings{jamieson_odin_II
     booktitle = {International Symposium on Field-Programmable Custom Computing Machines},
     pages = {149--156},
     year = {2010},
-    url = {http://dx.doi.org/10.1109/FCCM.2010.31},
+    doi = {10.1109/FCCM.2010.31},
 }
 
 @article{luu_vtr_7,
@@ -153,7 +173,6 @@ @article{luu_vtr_7
     pages = {1--30},
     publisher = {ACM},
     title = {{VTR 7.0: Next Generation Architecture and CAD System for FPGAs}},
-    url = {http://dl.acm.org/citation.cfm?id=2638850.2617593},
     volume = {7},
     year = {2014},
 }
@@ -184,7 +203,8 @@ @inproceedings{lamoureux_activity_estimation
     title = {Activity Estimation for Field-Programmable Gate Arrays},
     booktitle = {International Conference on Field Programmable Logic and Applications},
     pages = {1--8},
-    year = {2006}
+    year = {2006},
+    doi = {10.1109/FPL.2006.311199},
 }
 
 @article{ho_floating_point_fpga,
@@ -199,7 +219,6 @@ @article{ho_floating_point_fpga
     issn = {1063-8210},
     pages = {1709--1718},
     numpages = {10},
-    url = {http://dx.doi.org/10.1109/TVLSI.2008.2006616},
     doi = {10.1109/TVLSI.2008.2006616},
     acmid = {1721479},
     publisher = {IEEE Educational Activities Department},
@@ -240,7 +259,6 @@ @article{murray_timing_driven_titan
     pages = {10:1--10:18},
     articleno = {10},
     numpages = {18},
-    url = {http://doi.acm.org/10.1145/2629579},
     doi = {10.1145/2629579},
     acmid = {2629579},
     publisher = {ACM},
@@ -257,3 +275,12 @@ @inproceedings{murray_titan
     doi={10.1109/FPL.2013.6645503},
     month={Sept},
 }
+
+@manual{xilinx_virtex_6_clb,
+    title = {Virtex-6 FPGA Configurable Logic Block User Guide},
+    organization = {Xilinx Inc},
+    edition = {UG364},
+    month = {feb},
+    year = {2012},
+    url = {http://www.xilinx.com/support/documentation/user_guides/ug364.pdf},
+}