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Merge pull request #2317 from verilog-to-routing/setup_placer_seed
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Clean up and Document Placement
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vaughnbetz committed Jun 14, 2023
2 parents 02d433d + d88b444 commit c4156f2
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135 changes: 135 additions & 0 deletions doc/src/vpr/command_line_usage.rst
Original file line number Diff line number Diff line change
Expand Up @@ -821,6 +821,65 @@ Setting any of the following options selects `Dusty's annealing schedule <dusty_

**Default:** ``0.25``

.. option:: --place_cost_exp <float>

Wiring cost is divided by the average channel width over a net's bounding box
taken to this exponent. Only impacts devices with different channel widths in
different directions or regions.

**Default:** ``1``

.. option:: --RL_agent_placement {on | off}

Uses a Reinforcement Learning (RL) agent in choosing the appropiate move type in placement.
It activates the RL agent placement instead of using a fixed probability for each move type.

**Default:** ``on``

.. option:: --place_agent_multistate {on | off}

Enable a multistate agent in the placement. A second state will be activated late in
the annealing and in the Quench that includes all the timing driven directed moves.

**Default:** ``on``

.. option:: --place_agent_algorithm {e_greedy | softmax}

Controls which placement RL agent is used.

**Default:** ``softmax``

.. option:: --place_agent_epsilon <float>

Placement RL agent's epsilon for the epsilon-greedy agent. Epsilon represents
the percentage of exploration actions taken vs the exploitation ones.

**Default:** ``0.3``

.. option:: --place_agent_gamma <float>

Controls how quickly the agent's memory decays. Values between [0., 1.] specify
the fraction of weight in the exponentially weighted reward average applied to moves
which occured greater than moves_per_temp moves ago. Values < 0 cause the
unweighted reward sample average to be used (all samples are weighted equally)

**Default:** ``0.05``

.. option:: --place_reward_fun {basic | nonPenalizing_basic | runtime_aware | WLbiased_runtime_aware}

The reward function used by the placement RL agent to learn the best action at each anneal stage.

.. note:: The latter two are only available for timing-driven placement.

**Default:** ``WLbiased_runtime_aware``

.. option:: --place_agent_space {move_type | move_block_type}

The RL Agent exploration space can be either based on only move types or also consider different block types moved.

**Default:** ``move_block_type``


.. _timing_driven_placer_options:

Timing-Driven Placer Options
Expand Down Expand Up @@ -920,6 +979,82 @@ The following options are only valid when the placement engine is in timing-driv

Name of the post-placement timing report file to generate (not generated if unspecfied).


.. _noc_placement_options:

NoC Options
^^^^^^^^^^^^^^
The following options are only used when FPGA device and netlist contain a NoC router.

.. option:: --noc {on | off}

Enables a NoC-driven placer that optimizes the placement of routers on the NoC. Also, it enables an option in the graphical display that can be used to
display the NoC on the FPGA.

**Default:** ``off``

.. option:: --noc_flows_file <file>

XML file containing the list of traffic flows within the NoC (communication between routers).

.. note:: noc_flows_file are required to specify if NoC optimization is turned on (--noc on).

.. option:: --noc_routing_algorithm {xy_routing | bfs_routing}

Controls the algorithm used by the NoC to route packets.

* ``xy_routing`` Uses the direction oriented routing algorithm. This is recommended to be used with mesh NoC topologies.
* ``bfs_routing`` Uses the breadth first search algorithm. The objective is to find a route that uses a minimum number of links. This can be used with any NoC topology.

**Default:** ``bfs_routing``

.. option:: --noc_placement_weighting <float>

Controls the importance of the NoC placement parameters relative to timing and wirelength of the design.

* ``noc_placement_weighting = 0`` means the placement is based solely on timing and wirelength.
* ``noc_placement_weighting = 1`` means noc placement is considered equal to timing and wirelength.
* ``noc_placement_weighting > 1`` means the placement is increasingly dominated by NoC parameters.

**Default:** ``0.6``

.. option:: --noc_latency_constraints_weighting <float>

Controls the importance of meeting all the NoC traffic flow latency constraints.

* ``latency_constraints = 0`` means the latency constraints have no relevance to placement.
* ``0 < latency_constraints < 1`` means the latency constraints are weighted equally to the sum of other placement cost components.
* ``latency_constraints > 1`` means the placement is increasingly dominated by reducing the latency constraints of the traffic flows.

**Default:** ``1``

.. option:: --noc_latency_weighting <float>

Controls the importance of reducing the latencies of the NoC traffic flows.
This value can be >=0,

* ``latency = 0`` means the latencies have no relevance to placement.
* ``0 < latency < 1`` means the latencies are weighted equally to the sum of other placement cost components.
* ``latency > 1`` means the placement is increasingly dominated by reducing the latencies of the traffic flows.

**Default:** ``0.05``

.. option:: --noc_swap_percentage <float>

Sets the minimum fraction of swaps attempted by the placer that are NoC blocks.
This value is an integer ranging from [0-100].

* ``0`` means NoC blocks will be moved at the same rate as other blocks.
* ``100`` means all swaps attempted by the placer are NoC router blocks.

**Default:** ``40``

.. option:: --noc_placement_file_name <file>

Name of the output file that contains the NoC placement information.

**Default:** ``vpr_noc_placement_output.txt``

.. _router_options:

Router Options
Expand Down
15 changes: 15 additions & 0 deletions libs/libarchfpga/src/echo_arch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -322,6 +322,21 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
}
fprintf(Echo, "*************************************************\n\n");

//Router Connection List
if (arch->noc != nullptr) {
fprintf(Echo, "*************************************************\n");
fprintf(Echo, "NoC Router Connection List:\n");

for (auto noc_router : arch->noc->router_list) {
fprintf(Echo, "NoC router %d is connected to:\t", noc_router.id);
for (auto noc_conn_id : noc_router.connection_list) {
fprintf(Echo, "%d\t", noc_conn_id);
}
fprintf(Echo, "\n");
}
fprintf(Echo, "*************************************************\n\n");
}

//Architecture Power
fprintf(Echo, "*************************************************\n");
fprintf(Echo, "Power:\n");
Expand Down
10 changes: 0 additions & 10 deletions libs/libarchfpga/src/read_xml_arch_file.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4682,16 +4682,6 @@ static void ProcessNoc(pugi::xml_node noc_tag, t_arch* arch, const pugiutil::loc

if (noc_mesh_topology) {
processMeshTopology(noc_mesh_topology, loc_data, noc_ref);

for (auto i = noc_ref->router_list.begin(); i != noc_ref->router_list.end(); i++) {
std::cout << "router " << i->id << ": ";

for (auto j = i->connection_list.begin(); j != i->connection_list.end(); j++) {
std::cout << *j << ",";
}

std::cout << "\n";
}
} else {
noc_topology = pugiutil::get_single_child(noc_tag, "topology", loc_data, pugiutil::REQUIRED);

Expand Down
5 changes: 2 additions & 3 deletions vpr/src/base/SetupVPR.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -267,7 +267,6 @@ void SetupVPR(const t_options* Options,
vtr::out_file_prefix = Options->out_file_prefix;

/* Set seed for pseudo-random placement, default seed to 1 */
PlacerOpts->seed = Options->Seed;
vtr::srandom(PlacerOpts->seed);

{
Expand Down Expand Up @@ -600,7 +599,6 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts)
PlacerOpts->inner_loop_recompute_divider = Options.inner_loop_recompute_divider;
PlacerOpts->quench_recompute_divider = Options.quench_recompute_divider;

//TODO: document?
PlacerOpts->place_cost_exp = 1;

PlacerOpts->td_place_exp_first = Options.place_exp_first;
Expand Down Expand Up @@ -629,7 +627,6 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts)
PlacerOpts->delay_model_type = Options.place_delay_model;
PlacerOpts->delay_model_reducer = Options.place_delay_model_reducer;

//TODO: document?
PlacerOpts->place_freq = PLACE_ONCE; /* DEFAULT */

PlacerOpts->post_place_timing_report_file = Options.post_place_timing_report_file;
Expand Down Expand Up @@ -666,6 +663,8 @@ static void SetupPlacerOpts(const t_options& Options, t_placer_opts* PlacerOpts)
PlacerOpts->place_constraint_subtile = Options.place_constraint_subtile;
PlacerOpts->floorplan_num_horizontal_partitions = Options.floorplan_num_horizontal_partitions;
PlacerOpts->floorplan_num_vertical_partitions = Options.floorplan_num_vertical_partitions;

PlacerOpts->seed = Options.Seed;
}

static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysis_opts) {
Expand Down
7 changes: 5 additions & 2 deletions vpr/src/base/vpr_types.h
Original file line number Diff line number Diff line change
Expand Up @@ -1038,7 +1038,10 @@ enum class e_place_delta_delay_algorithm {
* When in CRITICALITY_TIMING_PLACE mode, what is the
* tradeoff between timing and wiring costs.
* @param place_cost_exp
* Power to which denominator is raised for linear_cong.
* Wiring cost is divided by the average channel width over
* a net's bounding box taken to this exponent.
* Only impacts devices with different channel widths in
* different directions or regions. (Default: 1)
* @param place_chan_width
* The channel width assumed if only one placement is performed.
* @param pad_loc_type
Expand All @@ -1050,7 +1053,7 @@ enum class e_place_delta_delay_algorithm {
* File to read pad locations from if pad_loc_type is USER.
* @param place_freq
* Should the placement be skipped, done once, or done
* for each channel width in the binary search.
* for each channel width in the binary search. (Default: ONCE)
* @param recompute_crit_iter
* How many temperature stages pass before we recompute
* criticalities based on the current placement and its
Expand Down

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