Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to…

…-routing

LICENSE.md

@@ -0,0 +1,69 @@
+# VTR License
+
+The software package "VTR" includes the software tools ODIN II, ABC, and VPR as
+well as additional benchmarks, documentation, and scripts. The authors of the
+various components of VTR retain their ownership of their tools.
+
+* With the exception of ABC and the benchmark circuits, all software,
+documents, and scripts in VTR, follows the standard MIT license described
+[here](http://www.opensource.org/licenses/mit-license.php) copied below for
+your convenience:
+
+The MIT License (MIT) Copyright (c) 2012 copyright Jason Luu, Jeffrey Goeders,
+Chi Wai Yu, Opal Densmore, Andrew Somerville, Kenneth Kent, Peter Jamieson,
+Jason Anderson, Ian Kuon, Alexander Marquardt, Andy Ye, Ted Campbell, Wei Mark
+Fang, Vaughn Betz, Jonathan Rose
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+
+* Terms and conditions for ABC is found
+[here](http://www.eecs.berkeley.edu/~alanmi/abc/copyright.htm) copied below
+for your convenience:
+
+Copyright (c) The Regents of the University of California. All rights reserved.
+
+Permission is hereby granted, without written agreement and without license or
+royalty fees, to use, copy, modify, and distribute this software and its
+documentation for any purpose, provided that the above copyright notice and the
+following two paragraphs appear in all copies of this software.
+
+IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
+DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF
+THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
+CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING,
+BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
+AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO PROVIDE MAINTENANCE,
+SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+
+The Verilog benchmark circuits are all open source but each have their own
+individual terms and conditions which are listed in the source code of each
+benchmark.
+
+Subject to these conditions, the software is provided free of charge to all
+interested parties.
+
+If you do decide to use this tool, please reference our work as references are
+important in academia.
+
+Donations in the form of research grants to promote further research and
+development on the tools will be gladly accepted, either anonymously or with
+attribution on our future publications.

README.md

@@ -68,8 +68,15 @@ Contributors
 
 Professors: Kenneth Kent, Vaughn Betz, Jonathan Rose, Jason Anderson, Peter Jamieson
 
-Graduate Students: Kevin Murray, Jason Luu, Oleg Petelin, Jeffrey Goeders, Chi Wai Yu, Andrew Somerville, Ian Kuon, Alexander Marquardt, Andy Ye, Wei Mark Fang, Tim Liu, Charles Chiasson
+Graduate Students: Kevin Murray, Jason Luu, Oleg Petelin, Jeffrey Goeders, Chi Wai Yu, Andrew Somerville, Ian Kuon, Alexander Marquardt, Andy Ye, Wei Mark Fang, Tim Liu, Charles Chiasson, Panagiotis Patros
 
 Summer Students: Opal Densmore, Ted Campbell, Cong Wang, Peter Milankov, Scott Whitty, Michael Wainberg, Suya Liu, Miad Nasr, Nooruddin Ahmed, Thien Yu, Long Yu Wang, Matthew J.P. Walker, Amer Hesson, Sheng Zhong, Hanqing Zeng
 
 Companies: Altera Corporation, Texas Instruments
+
+License
+=======
+
+Generally most code is under MIT license, with the exception of ABC which is
+distributed under its own (permissive) terms. Full license details can be
+found [here](LICENSE.md).

doc/vtr/tasks.rst

@@ -8,8 +8,22 @@ Tasks provide a framework for running the VTR flow on multiple benchmarks and ar
 A task specifies a set of benchmark circuits and architectures to be used.
 By default, tasks execute the :ref:`run_vtr_flow` script for every circuit/architecture combination.
 
+Example Tasks
+~~~~~~~~~~~~~
+* ``basic_flow``: Runs the VTR flow mapping a simple Verilog circuit to an FPGA architecture.
+
+* ``timing``: Runs the flagship VTR benchmarks on a comprehensive, realistic architecture file.
+
+* ``timing_chain``: Same as ``timing`` but with carry chains.
+
+* ``regression_mcnc``: Runs VTR on the historical MCNC benchmarks on a legacy architecture file. (Note: This is only useful for comparing to the past, it is not realistic in the modern world)
+
+* ``regression_titan\titan_small``: Runs a small subset of the Titan benchmarks targetting a simplified Altera Stratix IV (commercial FPGA) architecture capture
+
+* ``regression_fpu_hard_block_arch``: Custom hard FPU logic block architecture
+
 File Layout
-~~~~~~~~~~~~~~
+~~~~~~~~~~~
 
 All of VTR's included tasks are located here::
 

libarchfpga/ezxml.c

@@ -645,7 +645,7 @@ ezxml_t ezxml_parse_str(char *s, size_t len) {
 						(l) ? (char*)realloc(attr[l + 1], (l / 2) + 2) : (char*)malloc(2); /* mem for list of maloced vals */
 				strcpy(attr[l + 3] + (l / 2), " "); /* value is not malloced */
 				attr[l + 2] = NULL; /* null terminate list */
-				attr[l + 1] = ""; /* temporary attribute value */
+				attr[l + 1] = my_strdup(""); /* temporary attribute value */
 				attr[l] = s; /* set attribute name */
 
 				s += strcspn(s, EZXML_WS "=/>");
@@ -1076,14 +1076,14 @@ ezxml_error(ezxml_t xml) {
 
 /* returns a new empty ezxml structure with the given root tag name */
 ezxml_t ezxml_new(char *name) {
-	static char *ent[] = { "lt;", "<", "gt;", ">", "quot;", """,
+	static const char *ent[] = { "lt;", "<", "gt;", ">", "quot;", """,
 			"apos;", "'", "amp;", "&", NULL };
 	ezxml_root_t root = (ezxml_root_t) memset(malloc(sizeof(struct ezxml_root)),
 			'\0', sizeof(struct ezxml_root));
 
 	root->xml.name = name;
 	root->cur = &root->xml;
-	strcpy(root->err, root->xml.txt = "");
+	strcpy(root->err, root->xml.txt = my_strdup(""));
 	root->ent = (char**)memcpy(malloc(sizeof(ent)), ent, sizeof(ent));
 	root->attr = root->pi = (char ***) (root->xml.attr = EZXML_NIL);
 	return &root->xml;
@@ -1147,7 +1147,7 @@ ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off) {
 			sizeof(struct ezxml));
 	child->name = name;
 	child->attr = EZXML_NIL;
-	child->txt = "";
+	child->txt = my_strdup("");
 
 	return ezxml_insert(child, xml, off);
 }
@@ -1164,6 +1164,12 @@ ezxml_t ezxml_set_txt(ezxml_t xml, char *txt) {
 	return xml;
 }
 
+/* const char* version for string literals */
+ezxml_t ezxml_set_txt(ezxml_t xml, const char *txt) {
+    return ezxml_set_txt(xml, my_strdup(txt));
+}
+
+
 /* Sets the given tag attribute or adds a new attribute if not found. A value */
 /* of NULL will remove the specified attribute. Returns the tag given. */
 ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {
@@ -1220,6 +1226,12 @@ ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {
 	return xml;
 }
 
+/* const char* version for string literals */
+ezxml_t ezxml_set_attr(ezxml_t xml, const char *name, char *value) {
+    return ezxml_set_attr(xml, my_strdup(name), value);
+}
+
+
 /* sets a flag for the given tag and returns the tag */
 ezxml_t ezxml_set_flag(ezxml_t xml, short flag) {
 	if (xml)

libarchfpga/include/ezxml.h

@@ -30,10 +30,6 @@
 #include <stdarg.h>
 #include <fcntl.h>
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 #define EZXML_BUFSIZE 1024	/* size of internal memory buffers */
 #define EZXML_NAMEM   0x80	/* name is malloced */
 #define EZXML_TXTM    0x40	/* txt is malloced */
@@ -151,6 +147,7 @@ ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off);
 
 /* sets the character content for the given tag and returns the tag */
 ezxml_t ezxml_set_txt(ezxml_t xml, char *txt);
+ezxml_t ezxml_set_txt(ezxml_t xml, const char *txt);
 
 /* wrapper for ezxml_set_txt() that strdup()s txt */
 #define ezxml_set_txt_d(xml, txt) \
@@ -159,6 +156,7 @@ ezxml_t ezxml_set_txt(ezxml_t xml, char *txt);
 /* Sets the given tag attribute or adds a new attribute if not found. A value */
 /* of NULL will remove the specified attribute. Returns the tag given. */
 ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value);
+ezxml_t ezxml_set_attr(ezxml_t xml, const char *name, char *value);
 
 /* Wrapper for ezxml_set_attr() that strdup()s name/value. Value cannot be NULL */
 #define ezxml_set_attr_d(xml, name, value) \
@@ -180,7 +178,4 @@ ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off);
 /* removes a tag along with all its subtags */
 #define ezxml_remove(xml) ezxml_free(ezxml_cut(xml))
 
-#ifdef __cplusplus
-}
-#endif
 #endif				/* _EZXML_H */

libarchfpga/include/read_xml_util.h

@@ -22,11 +22,11 @@ char **GetNodeTokens(INP ezxml_t Node);
 char **LookaheadNodeTokens(INP ezxml_t Node);
 int CountChildren(INP ezxml_t Node, INP const char *Name,
 		INP int min_count);
-int GetIntProperty(INP ezxml_t Parent, INP char *Name,
+int GetIntProperty(INP ezxml_t Parent, INP const char *Name,
 		INP bool Required, INP int default_value);
-float GetFloatProperty(INP ezxml_t Parent, INP char *Name,
+float GetFloatProperty(INP ezxml_t Parent, INP const char *Name,
 		INP bool Required, INP float default_value);
-bool GetboolProperty(INP ezxml_t Parent, INP char *Name,
+bool GetboolProperty(INP ezxml_t Parent, INP const char *Name,
 		INP bool Required, INP bool default_value);
 #ifdef __cplusplus 
 }

libarchfpga/read_xml_arch_file.c

@@ -2248,7 +2248,7 @@ static void ProcessChanWidthDistrDir(INOUTP ezxml_t Node, OUTP t_chan * chan) {
 static void SetupEmptyType(void) {
 	t_type_descriptor * type;
 	type = &cb_type_descriptors[EMPTY_TYPE->index];
-	type->name = "<EMPTY>";
+	type->name = my_strdup("<EMPTY>");
 	type->num_pins = 0;
 	type->width = 1;
 	type->height = 1;

libarchfpga/read_xml_util.c

@@ -265,7 +265,7 @@ LookaheadNodeTokens(INP ezxml_t Node) {
 
 /* Find integer attribute matching Name in XML tag Parent and return it if exists.  
  Removes attribute from Parent */
-extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,
+extern int GetIntProperty(INP ezxml_t Parent, INP const char *Name,
 		INP bool Required, INP int default_value) {
 	const char * Prop;
 	int property_value;
@@ -274,14 +274,14 @@ extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,
 	Prop = FindProperty(Parent, Name, Required);
 	if (Prop) {
 		property_value = my_atoi(Prop);
-		ezxml_set_attr(Parent, Name, NULL);
+		ezxml_set_attr(Parent, my_strdup(Name), NULL);
 	}
 	return property_value;
 }
 
 /* Find floating-point attribute matching Name in XML tag Parent and return it if exists.  
  Removes attribute from Parent */
-extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,
+extern float GetFloatProperty(INP ezxml_t Parent, INP const char *Name,
 		INP bool Required, INP float default_value) {
 
 	const char * Prop;
@@ -291,14 +291,14 @@ extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,
 	Prop = FindProperty(Parent, Name, Required);
 	if (Prop) {
 		property_value = (float)atof(Prop);
-		ezxml_set_attr(Parent, Name, NULL);
+		ezxml_set_attr(Parent, my_strdup(Name), NULL);
 	}
 	return property_value;
 }
 
 /* Find bool attribute matching Name in XML tag Parent and return it if exists.  
  Removes attribute from Parent */
-extern bool GetboolProperty(INP ezxml_t Parent, INP char *Name,
+extern bool GetboolProperty(INP ezxml_t Parent, INP const char *Name,
 		INP bool Required, INP bool default_value) {
 
 	const char * Prop;
@@ -317,7 +317,7 @@ extern bool GetboolProperty(INP ezxml_t Parent, INP char *Name,
 			vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), Parent->line, 
 				"Unknown value %s for bool attribute %s in %s", Prop, Name, Parent->name);
 		}
-		ezxml_set_attr(Parent, Name, NULL);
+		ezxml_set_attr(Parent, my_strdup(Name), NULL);
 	}
 	return property_value;
 }

vpr/SRC/base/read_blif.c

@@ -682,7 +682,7 @@ static void add_subckt(bool doall, t_model *user_models) {
 			port_name = my_strdup(subckt_signal_name[i]);
 			pin_number = strrchr(port_name, '[');
 			if (pin_number == NULL) {
-				pin_number = "0"; /* default to 0 */
+				pin_number = my_strdup("0"); /* default to 0 */
 			} else {
 				/* The pin numbering is port_name[pin_number] so need to go one to the right of [ then NULL out ] */
 				*pin_number = '\0';

vpr/SRC/power/power.c

@@ -102,13 +102,13 @@ static void power_print_summary(FILE * fp, t_vpr_setup vpr_setup);
 //static void power_print_stats(FILE * fp);
 static void power_print_breakdown_summary(FILE * fp);
 static void power_print_breakdown_entry(FILE * fp, int indent,
-		e_power_breakdown_entry_type type, char * name, float power,
-		float total_power, float perc_dyn, char * method);
-static void power_print_breakdown_component(FILE * fp, char * name,
+		e_power_breakdown_entry_type type, const char * name, float power,
+		float total_power, float perc_dyn, const char * method);
+static void power_print_breakdown_component(FILE * fp, const char * name,
 		e_power_component_type type, int indent_level);
 static void power_print_breakdown_pb(FILE * fp);
 
-static char * power_estimation_method_name(
+static const char * power_estimation_method_name(
 		e_power_estimation_method power_method);
 
 /************************* FUNCTION DEFINITIONS *********************/
@@ -1536,7 +1536,7 @@ static void power_print_clb_detailed(FILE * fp) {
  }
  */
 
-static char * power_estimation_method_name(
+static const char * power_estimation_method_name(
 		e_power_estimation_method power_method) {
 	switch (power_method) {
 	case POWER_METHOD_UNDEFINED:
@@ -1822,7 +1822,7 @@ static void power_print_breakdown_pb(FILE * fp) {
 /**
  * Internal recurseive function, used by power_component_print_usage
  */
-static void power_print_breakdown_component(FILE * fp, char * name,
+static void power_print_breakdown_component(FILE * fp, const char * name,
 		e_power_component_type type, int indent_level) {
 	power_print_breakdown_entry(fp, indent_level,
 			POWER_BREAKDOWN_ENTRY_TYPE_COMPONENT, name,
@@ -1872,8 +1872,8 @@ static void power_print_breakdown_component(FILE * fp, char * name,
 }
 
 static void power_print_breakdown_entry(FILE * fp, int indent,
-		e_power_breakdown_entry_type type, char * name, float power,
-		float total_power, float perc_dyn, char * method) {
+		e_power_breakdown_entry_type type, const char * name, float power,
+		float total_power, float perc_dyn, const char * method) {
 	const int buf_size = 32;
 	char buf[buf_size];
 

vpr/SRC/power/power_cmos_tech.c

@@ -61,7 +61,7 @@ static int power_compare_buffer_sc_levr(const void * key_void,
 		const void * elem_void);
 static void power_tech_xml_load_components(ezxml_t parent);
 static void power_tech_xml_load_component(ezxml_t parent,
-		PowerSpicedComponent ** component, char * name,
+		PowerSpicedComponent ** component, const char * name,
 		float (*usage_fn)(int num_inputs, float transistor_size));
 /************************* FUNCTION DEFINITIONS *********************/
 
@@ -152,7 +152,7 @@ void power_tech_load_xml_file(char * cmos_tech_behavior_filepath) {
 }
 
 static void power_tech_xml_load_component(ezxml_t parent,
-		PowerSpicedComponent ** component, char * name,
+		PowerSpicedComponent ** component, const char * name,
 		float (*usage_fn)(int num_inputs, float transistor_size)) {
 	ezxml_t cur, child, gc, prev;